Chapter 05: I/O and Port Delays

What this chapter covers

STA only sees inside the chip. Paths that start at inputs or end at outputs depend on the external world. set_input_delay, set_output_delay, driving cells, and external loads describe that world so the tool can budget the on-chip portion. Virtual clocks are the usual reference when the external device’s clock is not a pin in this netlist.

Every chip-to-chip and chip-to-board interface — memories, buses, GPIO, high-speed links — needs I/O timing. Unconstrained ports are silently unchecked.

Worked example

If the external device launches 3 ns after its clock and the board consumes 1 ns, set_input_delay 4 -clock virt_clk [get_ports data_in] tells STA that 4 ns of the period is already used at the port. You still need a matching min delay for hold. Output delay is the external capture requirement seen from the output port.

A common misconception

Applying only max (setup) input delay and forgetting min, or referencing I/O to the wrong clock (core versus virtual versus forwarded strobe). Another trap is double-counting board delay in both the SDC and the other chip’s constraints so the system budget no longer closes.

Sample interview answers

Why are both max and min I/O delays required? Max models the late external arrival (setup). Min models the early arrival (hold). One number cannot cover both directions.

What is a virtual clock for? A timing reference that does not exist as a pin in this design, used to attach input/output delay when the other chip’s clock is outside the netlist.

What happens if a port has no I/O delay? That boundary path is not constrained. Internal WNS can look clean while the interface is untimed.

The paid chapter computes max/min I/O numbers, virtual-clock patterns, rise/fall splits, and interview questions for interface budgets.

STA view: Interface analysis · Next: False paths · Related: set_input_delay, set_output_delay