What this chapter covers

By default STA times every structural path. Some of those paths never carry timed functional data (unselected mux inputs, constants, CDC handled by synchronizers, test-only logic). set_false_path tells the tool to stop checking them. The dangerous failure mode is the opposite of most constraints: over-cutting hides a real path with no violation and no symptom.

Non-trivial chips have legitimate false paths, but this is also the most-abused exception. Reviews demand a reason, a tight -from/-to/-through, and a check that the exception did not swallow real endpoints.

Worked example

A synchronizer crossing that is already declared asynchronous in clock groups should not also need a wide false path through half the chip. A tighter form is set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b] only if that pair is truly not to be timed — and clock groups is usually the clearer intent. A mux whose select is tied to 0 can use case analysis instead of a blunt false path.

A common misconception

False-pathing a failing path to clean WNS. That is how real silicon escapes happen. Point-to-point false paths that use wildcards (*) are how entire domains disappear from timing.

Sample interview answers

When is a path genuinely false? When it cannot capture functional timed data in the mode you are analyzing — not merely because it is failing or noisy in the report.

Why is over-cutting worse than under-cutting? Under-cutting makes extra violations you can see. Over-cutting removes the check; the path can fail in silicon with a green report.

What should you inspect after adding a false path? Exception reports and unconstrained/endpoint coverage so the false path did not also disable a real startpoint/endpoint.

The paid PDF covers false-path versus case analysis versus disable_timing, precedence, verification reports, and 80 interview questions on exception discipline.

Next: Multicycle paths · Related: STA questions, SDC handbook

💡 Key Technical Topics Covered

  • set_false_path (-from, -to, -through)
  • Static Control Register Exception Constraints
  • Test Mode & Scan Path Timing Exceptions
  • Over-Constraining & False Path Debug Pitfalls

🎯 VLSI Physical Design Interview Questions Addressed

  • What is a false path in SDC and when should you apply it?
  • What is the difference between set_false_path -through vs -from/-to?
  • Why can an incorrect set_false_path cause silicon failure?