CHAPTER TWELVE

Clock Trunk Planning: A Coarse Spine Is Not a Finished Tree

By the end of this chapter you will know what a clock is, what a clock trunk is, and what a clock tree still has to do later. You will load a CTS constraint mapping file. You will grow clock-trunk endpoints inside shaped blocks. You will check the design before you grow a spine. You will choose the editable flavour or the push-down flavour on purpose. And you will treat a returned spine as a heartbeat, not as a finished clock tree.

Why this chapter matters in a real project

Think of a chip as a city of rooms. Power is already in the streets from Chapter 10. The data bus already has a map from Chapter 11. What the city still lacks is a shared heartbeat. That heartbeat is the clock. Every flip-flop that belongs to a clock must see the same repeating tick, or the rooms will disagree about “now.”

Sit with Nimbus-8 the morning after Chapter 11. The 128-bit CPU–NPU bus has a map through the leftover channel. VDD and VSS are metal. The rooms are shaped. And yet clk_cpu still has no agreed spine from the port to the cluster. A clock trunk is a coarse map for that heartbeat. It starts at the clock source. It ends at a clock-trunk endpoint. It is not a wire to every flip-flop. Clock tree synthesis, later, still grows those last twigs.

If you skip this chapter, two expensive things happen. Either clock tree synthesis invents a clock path through a room you needed for the bus, or you later discover that two NPU copies do not share a clock pin. The leftover 2.091 mm² = 2,091,000 µm² channel is still where this spine lives. The mesh on M4 and M5 is still not a clock layer you steal because it looks fat.

One more thing, because it will happen to you. You will type synthesize_clock_trunks. It will return 1. That means the spine command finished. It does not mean the feasibility check was clean. It does not mean every endpoint has a delay you would defend. It does not mean report_clock_trunk_qor is a number you would ship. Those are other commands.

Prerequisites

Chapter 11, because the leftover channel already holds a bus map and you must not park a clock spine through the ISP sofa. Chapter 10, because M4 and M5 already carry the 20 µm power mesh. Chapter 9, because blocks are shaped. Chapter 8, because a module is a name and a block is a physical room — trunk endpoints sit in rooms, not in names.

Multiply instantiated block, then MIB: two copies of the same drawing. On Nimbus-8 the two NPU copies share NPU_CORE. In this flow they are read-only. Their clock pins are placed by hand before you start. The library is nimbus8.dlib. The top is NIMBUS8.

How to read the numbers and the notation in this chapter

Read this table slowly. Every later command uses these words. If a word here is still fog, stop and read the row again before you type Tcl.

Learning objectives

After this chapter you will be able to:

1. Say what a clock, a period, a source, a sink, a trunk, and an endpoint are, in plain words.
2. Write a CTS_CONSTRAINT mapping file for Nimbus-8 and load it, knowing that without -reset maps append.
3. Place MIB clock pins by hand before any trunk command, because copies are read-only in this flow.
4. Run block-level synthesize_clock_trunk_endpoints with -clocks, and plant a black-box endpoint with set_clock_trunk_endpoints.
5. Read report_clock_trunk_endpoints, including the dominant * and the -script write-back.
6. Run check_design_for_clock_trunk_planning -clock (no s) before the top-level spine.
7. Set optional CTP pin constraints with -cells, legal sides, and a feedthrough policy you said out loud.
8. Choose optimize_subblocks or push_down on purpose, and name the documented spelling conflict.
9. Synthesize with the plural command, then taste with report_clock_trunk_qor, without treating return 1 as CTS.

The beginner’s mental model

A subway trunk line is not every streetcar

Hold a city map that shows only the trunk line from the central station to the last interchange. The twigs that run from that interchange to every house are someone else’s drawing. A clock trunk is that trunk line. The source is the clock port. The last interchange is the endpoint. The houses are flip-flops. Clock tree synthesis still owns the houses.

The analogy stops being silicon quite quickly, and that is the point. An endpoint can have a delay behind it that is only an estimate. Two NPU copies can share one drawing and still disagree about a clock pin you never placed. A cheerful return value means the spine command finished. Tasting is report_clock_trunk_qor.

The precise engineering model

The database already has shaped blocks, a leftover channel, a compiled power grid, and a bus map. Clock trunk planning adds a second spine on that geometry. You load CTS constraints through a mapping file. You grow endpoints inside blocks — or you plant them by hand on a black box. You check whether the design can even accept a trunk. You optionally fence the sides that may take a clock pin. Then you synthesize a top-level spine that compensates those endpoint delays and tries to share a common path between blocks that talk to each other.

Two flavours exist and they are not a style choice. plan.clock_trunk.flow_control set to optimize_subblocks treats blocks as editable. That is the THO flavour: it supports multiple levels of physical hierarchy and multivoltage, and it has three named stages. Set to push_down, blocks are read-only, CTS parks cells on top of them, and push_down_clock_trunks commits the topology. Push-down does not support MPH or multivoltage. A nearby flow sentence writes pushdown without the underscore. The command-page example writes push_down. New Tcl uses the underscore. Confirm with man.

The practical loop is kind to beginners. Write the mapping file. Place MIB clock pins. Grow block endpoints. Report them. Check feasibility. Optionally set CTP sides. Choose a flavour and read it back. Synthesize. Taste. Four small walks are easier to debug than one giant one.

Concepts built from first principles

Part 1 — What a trunk actually is

Do not start with a command. Start with the thing the command is trying to build. If you cannot point at a source, a walk, a door, and a last station on a sketch, the Tcl will only hide the fog.

What a clock is

A digital chip does not think in continuous time. It thinks in ticks. A clock is a repeating electrical tick that tells flip-flops when to capture a new value. Frequency is how many ticks happen each second. We write it in gigahertz. One gigahertz is one thousand million ticks per second. Period is the time from one tick to the next. Period is one divided by frequency.

On Nimbus-8 the teaching clock is clk_cpu at 1.60 GHz. Period = 1 / 1.60 GHz = 0.625 ns = 625 ps. Every flip-flop on that clock must finish its work inside that 625 ps window. If the clock arrives late at one room and early at another, the rooms disagree about “now.” That disagreement is why we plan a spine instead of hoping the later tree will invent a fair path.

The source is the clock port: the pin or port where the tick enters the design you are planning. The sink is a cell that uses that tick. The usual sink is a D flip-flop. Query the source with get_ports. Query the clock object with get_clocks. Teaching names in this book are stand-ins. On a real netlist you ask the design. You do not type a name from memory.

What a trunk is, and what a tree still is

If you wired the clock port straight to every flip-flop, two things would go wrong. The wire would be huge. And rooms that talk to each other would not share a common walk, so their clocks would skew in ways you cannot budget. A clock trunk is the coarse answer. It is a shared spine from the source to a small number of last stations, called endpoints. Buffers or inverters on that spine are anchor cells. They strengthen the tick so it can travel across leftover glue without dying.

A clock tree is the later, finer drawing. Clock tree synthesis (CTS) still grows twigs from each endpoint to the flip-flops behind it. This chapter does not run CTS to completion. It gives CTS a spine to honour. If you treat the trunk as “the clock is done,” you will ship a map and call it a tree.

Say it out loud: trunk first, tree later. The command that grows the trunk is synthesize_clock_trunks — plural. The flow picture nearby writes the singular. The singular has no command page. New Tcl uses the plural. Confirm with man.

The six names on one spine

The flow picture of this step uses six names. Keep them apart. Mixing any two is how a later report becomes a mystery.

1. Clock port. The source. Gold in the figures. On Nimbus-8 you query it; you do not invent clk_cpu as a typed string you hope exists.
2. Top-level clock-trunk arc. The walk across leftover glue, from the port toward a block. This is the teal spine in the leftover 2.091 mm² channel.
3. Block clock pin. The door into a room. The clock enters CPU_CLUSTER here. A door is not a last station.
4. Block-level clock-trunk arc. The walk inside that room, from the door toward the endpoint. Still planning. Still not every flip-flop.
5. Clock-trunk endpoint. The last station this chapter owns. A pin or port with a phase delay annotated toward the sinks. The delay is an estimate of how long the later twigs will take.
6. Feedthrough pin. A visit. The clock walks through a room that is not the destination. A buffer in that middle room is not a sink and not an endpoint.

Flip-flops remain CTS’s problem. Pin assignment for every bundle remains Chapter 13. This chapter may place some clock pins as a consequence of the spine. That is not the pin-assignment chapter.

The teaching delay, and the four clocks on Nimbus-8

Phase delay sits behind the endpoint, toward the sinks. It is not the period. It is not signoff insertion delay. On Nimbus-8 the teaching number is 0.200 ns = 200 ps. That is about one third of the 625 ps clk_cpu period. We choose a third so you can see it on a ruler. We label it an estimate so you do not ship it.

A nearby command-page example uses -delay 20. If the unit is nanoseconds, that is 20,000 ps. On a 625 ps period that is thirty-two ticks of fiction. Do not copy it. If you omit -delay, the trunk planner estimates the number. Saying the number out loud with both units is the grown-up move.

Nimbus-8 has four named clocks. The teaching spine today is the first one. The others still exist, and you still query them.

Do not confuse these

Part 2 — Constraints and the mapping file

Before a trunk can exist, both the block and the top need CTS-quality constraints. Constraints are rules the later tree must obey, used now so the spine is realistic. They include maximum capacitance, maximum transition, ignored layers, clock-tree reference cells, a driving cell, and nondefault routing rules. Those settings live in Tcl files. You do not type them as a pile of one-liners in the trunk session. You keep them in files, one file per reference block.

The mapping file is a table of contents. Each line says: this reference owns this kind of file. The keyword for this chapter is CTS_CONSTRAINT. Other kinds exist — SDC, UPF, PG — and they are not this cook. Load the map with:

# Teaching map. One CTS file per reference, including the top
icc2_shell> set_constraint_mapping_file -reset ./ctp_mapfile

The file itself is ordinary text. Each line is block_design_name constraint_type file_name. Teaching lines:

# ctp_mapfile
CPU_CLUSTER  CTS_CONSTRAINT  constraints/cpu_ctp.tcl
NPU_CORE     CTS_CONSTRAINT  constraints/npu_ctp.tcl
ISP          CTS_CONSTRAINT  constraints/isp_ctp.tcl
SOC_PERIPH   CTS_CONSTRAINT  constraints/soc_ctp.tcl
NIMBUS8      CTS_CONSTRAINT  constraints/top_ctp.tcl

Read the reset rule twice. Without -reset, a second load appends. That is how you silently own two CTS files for the same block. With -reset and a filename, the new map replaces. -reset alone clears. Block-level trunk planning will not start for a block that has no CTS_CONSTRAINT line. Virtual clocks are skipped. A block clock whose master cannot be traced to a top-level clock is ignored.

Inside those Tcl files you set layers with set_ignored_layers. On Nimbus-8 you do not steal M4 and M5. Those layers already hold the power mesh from Chapter 10. You do not invent a layer. You query the library, you write a minimum and a maximum you would defend, and you read the option back. The leftover channel is geometry. The layers are a CTS constraint, not a feeling about fat metal.

Part 3 — The MIB prior

A multiply instantiated block, then MIB, is two copies of the same drawing. On Nimbus-8, u_npu_core_0 and u_npu_core_1 both use the reference NPU_CORE. In this flow those copies are read-only. The tool will not invent a clock pin on a drawing you share. You place both clock pins by hand before you start. That is not a style. It is a prior.

Propagating a topology plan in Chapter 11 copied a bus map. It did not place a clock pin. Alignment in Chapter 11 checked rows and tracks. It did not place a clock pin. Do this first, then grow endpoints. Even if today’s teaching spine is only clk_cpu, you still place the NPU clock pins, because clk_npu is the MIB lesson and you will need that prior.

Part 4 — Block-level endpoints

Block-level planning answers a simple question: for this room, where should the last station sit, and how long will the later twigs take? The command estimates clock latency and inserts anchor cells. synthesize_clock_trunk_endpoints computes seed locations for clock ports, creates endpoints, and annotates phase delay. It uses clock tree synthesis as a measuring tape, based on block size, sink count, driving cell, and the CTS constraints you just mapped. If the block clock ports are already placed or fixed, seed-finding is skipped. The command supports multithreading. Prerequisites: blocks are shaped, and top-level flip-flops are placed.

The flag here is -clocks, with an s. Confirm the clock with get_clocks before you pass it.

# -clocks takes the s. Confirm the clock with get_clocks
icc2_shell> synthesize_clock_trunk_endpoints \
    -blocks {CPU_CLUSTER NPU_CORE ISP SOC_PERIPH} \
    -clocks [get_clocks clk_cpu]

For a black box you cannot synthesize, plant the endpoint by hand. The flag on this command is -clock, no s. Teaching delay 0.200 ns = 200 ps. Confirm the pin with get_pins.

# Teaching delay 0.200 ns = 200 ps. Confirm the pin with get_pins
icc2_shell> set_clock_trunk_endpoints \
    [get_pins {u_cpu_cluster/clk}] -clock [get_clocks clk_cpu] \
    -delay 0.200

A nearby command-page example uses -delay 20. That is twenty nanoseconds. On a 625 ps period that is thirty-two cycles of fiction. Do not copy it. If you omit -delay, the phase delay is undefined and the trunk planner estimates it.

Report what you just grew. Dominant endpoints — worst downstream phase delay from a given block clock pin — are marked *. Dominance is per clock and per corner; a winner in one corner may lose in another. Read the star. Do not assume last week’s winner is this corner’s winner.

icc2_shell> report_clock_trunk_endpoints -clock [get_clocks clk_cpu]
icc2_shell> report_clock_trunk_endpoints -script

remove_clock_trunk_endpoints takes them back off a pin, a clock, a corner, or everything. Default without a pin list is the wide broom again.

Buffers can sit on the shared walk before the endpoint, or only on the branches after it. Branch buffers live in the estimate. They are not the spine. Shared buffers before the endpoint are the spine’s business. Keep that cut when you read a schematic.

Part 5 — Feasibility before the spine

After settings, before synthesize_clock_trunks, run a named check. The command is check_design_for_clock_trunk_planning. This is not check_topology_feasibility from Chapter 11. It is a different command. Run it after you have set the trunk options, and before you grow the top-level spine. The flavour you chose — editable or push-down — changes which problems it will catch.

icc2_shell> check_design_for_clock_trunk_planning \
    -clock [get_clocks clk_cpu] -summary

The checks have names and message IDs. Read the ID. Repair the object it names. Adding a buffer will not change a Frame view. Adding a corridor will not give a block a location.

Read the ID. Fix that object. Then run the check again. Then synthesize.

Part 6 — Abstracts, when the child is light

Sometimes the child is too heavy to keep fully open at the top. An abstract is a lighter stand-in. Top-level trunk planning can run against abstracts. The order is: create them, prepare the hierarchy, synthesize, then commit. The prepare/commit command is synthesize_clock_trunk_setup_hier_context.

icc2_shell> set_editability -value true -blocks *
icc2_shell> create_abstract -blocks [get_blocks {CPU_CLUSTER NPU_CORE}]
icc2_shell> synthesize_clock_trunk_setup_hier_context -init
# ... synthesize_clock_trunks here ...
icc2_shell> synthesize_clock_trunk_setup_hier_context -commit

A nearby example types set_editability with no arguments. Do not copy that. -value and a block list are how you actually enable a child. A nearby flow example also writes -host_options on this command. The command page writes -host_option. New Tcl uses the singular. A Frame view is not an abstract you forgot to create. Feasibility will tell you if the view is wrong. Listen before you synthesize.

Part 7 — CTP pin constraints

Optional, and additive. After block-level endpoints you may fence which sides of a block may take a clock pin or a feedthrough cut. Think of it as telling the later pin placer, “clocks may land on this edge, in this window.” place_pins later honours these. They take priority over set_block_pin_constraints and set_individual_pin_constraints for this flow. Disabled blocks, via set_editability, are ignored.

# CPU leftover faces side 3. Offset 0 to 800 um on that edge
icc2_shell> set_ctp_constraints -cells [get_cells u_cpu_cluster] \
    -sides {3} -offset {0 800}
icc2_shell> report_ctp_constraints -cells [get_cells u_cpu_cluster]

The command is additive: later calls keep what you do not override. These constraints take priority over set_block_pin_constraints and set_individual_pin_constraints for this flow. Disabled blocks, via set_editability, are ignored. remove_ctp_constraints without -cells clears every block. It does nothing to a block you disabled. place_pins later honours these fences.

Part 8 — Top-level synthesis

Now the spine. Prerequisites the command page lists: blocks shaped, block clock ports placed, top-level flip-flops placed, endpoints identified with phase delays. synthesize_clock_trunk_endpoints is how you usually get those delays. Then choose a flavour and read it back. Reading it back is not decoration. Hidden defaults are how two people in a room run two different flows.

icc2_shell> set_app_options -name plan.clock_trunk.flow_control \
    -value optimize_subblocks
icc2_shell> set_app_options -name plan.clock_trunk.enable_new_flow \
    -value true
icc2_shell> report_app_options plan.clock_trunk.flow_control

For multiple levels of physical hierarchy, also set plan.clock_trunk.enable_mph_constraints to true and read it back. Nimbus-8’s CPU cluster has children inside it, so this is not a toy option. To allow feedthroughs on clock nets, set plan.pins.exclude_clocks_from_feedthroughs to false — if it is true, the tool will not create clock feedthroughs. Read that one back too. Remove topological pin-feedthrough constraints with remove_topological_constraints -all, and individual pin constraints with remove_individual_pin_constraints, before the spine so old fences do not fight the new map. The engine still honours block feedthrough enables, editability, allowed sides, routing blockages, and clock metal assignments.

Optionally prefix the cells the trunk inserts, so you can find them later in the netlist:

icc2_shell> set_app_options \
    -name cts.common.user_instance_name_prefix \
    -value ICC2_TOP_CTP_

Then check. Then synthesize. The command is plural. The flow picture writes the singular. The singular has no command page. New Tcl uses the plural.

icc2_shell> check_design_for_clock_trunk_planning \
    -clock [get_clocks clk_cpu] -summary
icc2_shell> synthesize_clock_trunks -clock [get_clocks clk_cpu]

The default pin-constraint script is read_pin_constr_place_pins.tcl. You may rename it with plan.clock_trunk.topo_constr_pin_place_script_name. Read the option back rather than asserting a remembered default.

Part 9 — Push-down flavour

If you chose read-only blocks, the sequence is flavour, check, synthesize, then push. Push-down means: grow the spine on top of rooms you must not edit, then push the trunk cells into those rooms that allow feedthroughs. It is a different rulebook from THO. Do not mix their flags.

icc2_shell> set_app_options -name plan.clock_trunk.flow_control \
    -value push_down
icc2_shell> report_app_options plan.clock_trunk.flow_control
icc2_shell> check_design_for_clock_trunk_planning -clock [get_clocks clk_cpu]
icc2_shell> synthesize_clock_trunks -clock [get_clocks clk_cpu]
icc2_shell> push_down_clock_trunks -clock [get_clocks clk_cpu]

The command pushes those cells into blocks that allow feedthroughs, creates the feedthroughs, and places the new ports. A See-also line nearby names create_block_pin_constraint. The flow you already have uses set_block_pin_constraints -allow_feedthroughs. Do not invent a third verb. Confirm with man.

This flavour does not consider move bounds or blockages inside first-level blocks. It does not support multiple levels of physical hierarchy. It does not support multivoltage. If Nimbus-8 needs either, you are in the THO flavour, not this one. This is also not push_down_objects from Chapter 11. Different object, different command.

Part 10 — Taste, incremental, and what this chapter does not finish

QoR of a trunk is not the heartbeat. Heartbeat is return 1. Taste needs ingredients: derates applied, then estimate_timing, then the report.

icc2_shell> report_clock_trunk_qor -clock [get_clocks clk_cpu]

The first call may trigger a full or incremental timing update. Later calls do not, unless the netlist or constraints changed. Apply derates. Run estimate_timing. Then taste.

Budgeting can inherit the spine: compute_budget_constraints -latency_targets estimated -balance true. That pair is required together. Writing the budget out and looking for -crp is working knowledge. Full budgeting is a later chapter. Clock feedthrough ports created by the spine need to be treated as clocks so they inherit CTS constraints: plan.budget.add_missing_feedthrough_clocks and plan.budget.include_feedthrough_clocks set true, then split_constraints. That is a bridge, not this cook.

Incremental synthesize_clock_trunks -incremental honours constraints you changed since the last full run. You may subset clocks. A full run must exist first. The GUI has a Clock Trunk Planning panel — View → Flylines → Clock Trunk Planning — for looking, not for replacing the commands you just learned.

Inputs, outputs, and readiness

Guided tool workflow

One continuous worked example

Nimbus-8, still. Core 3.20 mm × 3.20 mm = 10.24 mm² = 10,240,000 µm². Channel 2.091 mm² = 2,091,000 µm². Teaching spine: clk_cpu at 1.60 GHz = 625 ps, port through leftover glue into CPU_CLUSTER. Teaching endpoint delay 0.200 ns = 200 ps, an estimate, about a third of the period. Mesh on M4/M5 stays. Bus map on M3/M6 stays.

Query clk_cpu. Place clock pins on u_npu_core_0 and u_npu_core_1 by hand — you will need that prior even if today’s spine is only clk_cpu. Write ctp_mapfile with CTS_CONSTRAINT for each reference, including NIMBUS8. Load it with -reset. Grow endpoints for clk_cpu on the four references. Report them. Check feasibility with -clock and -summary. Optionally fence CPU side 3, the leftover face, with offset 0 to 800 µm. Set optimize_subblocks, read it back. Allow clock feedthroughs if you mean them. Synthesize the plural command. Estimate timing. Read QoR. Quiet success in this story is return 1 while a TL-130 still says a child has no location, or while QoR still shows a path you have not tasted. Read the line. Do not argue with the heartbeat.

Failure modes and debugging

Hands-on mini lab — Procyon-5

Procyon-5 is a new design, not Nimbus-8. The core is a square 800 µm = 0.800 mm on each side, so an area of 0.640 mm² = 640,000 µm². Two committed blocks sit left and right with a leftover strip between them. One clock, 400 MHz = 2,500 ps. Teaching endpoint delay 0.400 ns = 400 ps. No MIB in this lab. Sketch source, door, and endpoint on paper before you type.

Steps.

1. Query the clock. Write a mapping file with CTS_CONSTRAINT for both block references and the top. Load it with -reset.
2. Confirm top-level flip-flops are placed and blocks are shaped.
3. Run synthesize_clock_trunk_endpoints -clocks on both references. Do not type -clock here.
4. Report endpoints. Record the dominant * delay in picoseconds and nanoseconds.
5. Run check_design_for_clock_trunk_planning -clock ... -summary. Do not type -clocks.
6. Set plan.clock_trunk.flow_control to optimize_subblocks and read it back. Do not type pushdown.
7. Synthesize with the plural command. Estimate timing. Report QoR.

Expected observations. Endpoints exist before the spine. -clocks and -clock are different flags. Return 1 after synthesize can coexist with a QoR path you have not yet read. A 400 ps endpoint on a 2,500 ps period is an estimate, not a tree.

Verification checklist. Mapping used -reset; flags match each command page; flavour was read back; QoR followed estimate_timing; no conclusion rests only on return 1.

Stretch. Repeat the lab in push-down flavour with push_down. Confirm -from is rejected or inapplicable. Push down. Compare the two QoR reports without declaring a winner from the heartbeat.

Interview preparation

Chapter close

Sign-off checklist for this planning stage

1. You can point at source, door, endpoint, and feedthrough on a sketch.
2. Clock ports were queried, not invented.
3. MIB clock pins were placed by hand on both NPU copies.
4. Mapping file has CTS_CONSTRAINT for every reference you ran, loaded with -reset if it replaced.
5. Ignored layers do not steal M4/M5; the leftover channel is still the spine’s geometry.
6. Endpoints exist; delays are numbers with units; dominant * was read.
7. Feasibility used -clock, not -clocks, and TL messages are empty or explained.
8. Flavour is optimize_subblocks or push_down, read back, not mixed.
9. Synthesize used the plural command; return 1 was followed by estimate_timing and QoR.
10. CTP pin sides, if used, started at 1, never 0, and CPU leftover used side 3.
11. Pin assignment for every bundle was not mixed into this script.

Key-concept flashcards

Compact glossary

Five-question self-check

Hamal-3 has a core that is a square 1,200 µm = 1.200 mm on each side, so an area of 1.44 mm² = 1,440,000 µm². It has two clocks. Teaching endpoint delay is 0.300 ns = 300 ps.

1. You have a top-level clock clk_a and a block clock with a different name. Which endpoint flag associates them, and which flag is mutually exclusive with it?
2. A flow note says synthesize_clock_trunk -to pin_check. What do you type instead, and which three stages exist in THO flavour?
3. You set flow_control to pushdown and the tool rejects it. What token do you use, and which two capabilities does that flavour not support?
4. Block-level CTP on Hamal-3 does nothing for the second clock. Name the mapping-file cause and the reset rule.
5. Hamal-3 uses a 300 ps endpoint delay. If someone copied -delay 20 from an example, by what factor is that delay wrong against 300 ps, assuming nanoseconds?

Answers.

1. -auto_clock connected | local | all on set_clock_trunk_endpoints or on synthesize_clock_trunk_endpoints. It is mutually exclusive with -clock / -clocks. Query both clocks first.

2. Type synthesize_clock_trunks (plural) and a real stage token such as -to pin_constr_generation. The three THO stages are pin_constr_generation, read_pin_constr_and_place_pins, and clock_trunk_synthesis. Confirm with -list_only. There is no pin_check.

3. push_down. That flavour does not support multiple levels of physical hierarchy and does not support multivoltage. -from/-to do not apply. Confirm with man.

4. No CTS_CONSTRAINT line for that reference, or a second load appended the wrong file. Load with -reset when you mean replace. Block-level CTP does not start without the keyword.

5. 20 ns = 20,000 ps. 20,000 / 300 ≈ 67 times the teaching delay. Units first, then the copy. Do not import 20 onto Hamal-3.

Why Chapter 13 follows

The leftover channel now has a bus map and a clock spine, and the mesh still holds power. What the chip still lacks is a complete, constrained placement of every block pin the router will honour. That is pin assignment. It is not a tail on synthesize_clock_trunks. This chapter ends with clocks. The next begins at the sides of the rooms.