CHAPTER ELEVEN

Global Planning: The Channel You Left Is Where the Buses Live

By the end of this chapter you will be able to group bus bits into supernets and bundles; to write a net estimation rule that does not sit on the power mesh; to turn that bundle into a topology plan of nodes and edges; to check the plan against the netlist before you optimize; and to treat a routing corridor as a nudge, not a locked door.

Why this chapter matters in a real project

Sit with Nimbus-8 the morning after Chapter 10. VDD and VSS are metal. The ring walks M7 and M8. The mesh walks M4 and M5 at 20 µm. The cells can drink. And yet the chip still cannot talk to itself. The 128 bits that must run from the CPU cluster to an NPU copy have no agreed path through the leftover rooms. That leftover is not spare junk. It is 2.091 mm² = 2,091,000 µm² of channel, about a fifth of the 10.24 mm² = 10,240,000 µm² core, left empty on purpose so buses and glue can live there.

If you skip this chapter, two things happen and both are expensive. Either the router invents a bus path through a room you needed for something else, or you later spend a week drawing feedthroughs by hand. Global planning is the grown-up version of “which corridor does this bus walk?” You draw the map first. You check the map against the netlist. Only then do you ask the tool to walk it.

One more thing, because it will happen to you. You will type optimize_topology_plans. It will return 1. That means the walk finished. It does not mean the map matched the netlist, that every assigned pin sits inside a corridor, or that two NPU copies still share one drawing. Those are other commands.

Prerequisites

Chapter 10, because the mesh already occupies M4 and M5 and you must not park a bus on it. Chapter 9, because the rooms are shaped and the leftover channel is a measured number, not a feeling. Chapter 8, because a module is a name and a block is a physical room — topology nodes sit in rooms. Chapter 2, for the habit of reading back what you just set. The library is nimbus8.dlib. The top is NIMBUS8. Multiply instantiated block, then MIB: the two NPU copies share NPU_CORE.

How to read the numbers and the notation in this chapter

Learning objectives

After this chapter you will be able to:

1. Build a supernet from a queried driver and load, then bundle the bits.
2. Write a net estimation rule on teaching layers that do not steal the power mesh, and report it back.
3. Create a default topology plan for a named bundle, and know the command is plural.
4. Run check_topology_plans with a mode from the command page, not from a flow-picture nickname.
5. Tell a matching feasibility path from a missing-node mismatch.
6. Optimize, then implement repeaters, without treating return 1 as tapeout.
7. Propagate a plan onto the second NPU copy and check MIB alignment before push-down.
8. Draw a routing corridor, read whether it covers pins, and globally route only the planned nets.

The beginner’s mental model

A subway map is not the rails

Hold a subway map next to a photograph of the tunnel. The map says “these stations, in this order, under these streets.” The photograph is dirt, concrete, and steel. A supernet names who is travelling. A bundle says they travel together. A topology plan is the map: nodes where the bus stops in a room, edges where it walks the corridor. optimize_topology_plans is the crew that walks the map and chalks repeater sites. None of that is the finished rails in the street.

The analogy stops being silicon quite quickly, and that is the point. A map can skip a station that the netlist still visits. A corridor can leave a pin outside its fence. Two NPU copies can share one drawing and still disagree about a track offset. A cheerful return value means the crew finished the walk. Tasting is a different command.

The precise engineering model

The database already has blocks, a leftover channel, and a compiled power grid. Global planning adds a second language on top of that geometry. A supernet is a tracing: start at a driver pin, stop at one or more load pins, walk transparently through repeaters and through cells you marked as transparent. A bundle is a homogeneous group of those tracings, so 128 bits can be ordered and planned as one family. A net estimation rule is the recipe the plan will eat: preferred layers, a buffer cell, a spacing in micrometres. A topology plan is then a graph. Nodes sit in rooms. Edges connect them. If the bundle already contains feedthroughs, the tool plants nodes inside those rooms when it builds the base plan.

Why bother? Because the traditional path — place pins, punch feedthroughs, sprinkle buffers, route the bus, each with its own constraint dialect — forces you to become five different operators. Unified topology constraints keep the intent in one object you can create, check, refine, optimize, write out, and propagate onto a multiply instantiated block.

The practical loop is kind to beginners. Query the pins. Make the supernet and the bundle. Write the NER and report it. Create the default plan. Check it in pre_optimization. Refine if the walk is long. Optimize. Check it in post_optimization. If you also need a geometric nudge, add a routing corridor and globally route only those nets. Insert repeaters on that route. Allow feedthroughs. Push down. Legalise. Repair with ECO routing. Four small walks are easier to debug than one giant one.

Do not confuse these

Concepts built from first principles

Part 1 — Supernets and bundles

Start with one honest question: which bits travel together, from which driver, to which loads? A supernet answers that. You may give it one anchor pin or port, and the tool traces the physical hierarchy of that anchor. Or you give it a start and a stop. Or you give it one start and several stops. The start must be a driver. The stops must be loads. Both ends must sit in the same physical hierarchy. If a hierarchical term is offered, the tool picks the driver or the load for you — but you still queried the pin first, you did not invent it.

On Nimbus-8 the teaching bus is 128 bits from the CPU cluster toward an NPU copy, through the leftover channel. Do not type pin names from memory. Ask the design.

# Confirm driver and load pins with get_pins before you type them
icc2_shell> set cpu_drv [get_pins {u_cpu_cluster/cpu_npu_data_w[0]}]
icc2_shell> set npu_ld  [get_pins {u_npu_core_0/cpu_npu_data_r[0]}]
icc2_shell> create_supernet -name nimbus_cpu_npu -start $cpu_drv -stop $npu_ld

Those pin names are teaching stand-ins. Your netlist will differ. The shape of the command will not. -reuse is a different shape: it may be specified only with a pin-or-port anchor, not with -start / -stop. If a supernet with the same segments already exists, -reuse keeps it. Otherwise it creates. Default is false.

Repeaters are already transparent. Other cells are not, until you say so. set_supernet_exceptions marks pins, cells, or reference cells as transparent, or disables that marking. Hierarchical cells, library cells, and excluded cells are the vocabulary. You do this before the tracing, not after you are surprised.

A bundle is then the group. create_bundle -name nimbus_cpu_npu_bus with no objects makes an empty named box, which is legal and useless. Pass the supernets you just made. Or let create_bundles_from_patterns match net-name groups. That command’s default is eight or more bits. A nibble of four will not bundle until you lower -minimum_nets. You can ignore braces, brackets, angle brackets, underlines, colons, or parentheses in the names. You can sort ascending or descending. You can cap the maximum. Prefix matching is how you keep the CPU–NPU family from swallowing an unrelated 128-bit test bus.

# Either name the supernets, or match a verified prefix. Do not run both.
icc2_shell> create_bundle -name nimbus_cpu_npu_bus [get_supernets nimbus_cpu_npu*]
# create_bundles_from_patterns -net_name_prefix cpu_npu_data -minimum_nets 128

Part 2 — Net estimation rules

Before a topology plan can exist, it needs a recipe. A net estimation rule names the preferred layers, the buffer or inverter you want along the walk, the spacing between those buffers, and the spacing between pipeline registers. Horizontal and vertical may differ for layer. They must be set together: -horizontal_value comes with -vertical_value. A single -value applies to both directions. Report the rule. Do not trust the type-in.

On Nimbus-8 the power mesh already owns M4 and M5. M1 is rails. M2 is the dense signal street at 0.048 µm. The teaching bus therefore lives on M3 left-right and M6 up-down. That is a teaching choice you confirm against the library, not a law of physics. Buffer spacing 500 µm and register spacing 1,200 µm are the teaching distances. The buffer cell is whatever get_lib_cells says is a legal buffer in this library. Do not copy a cell name from another chip.

# Teaching NER. Confirm layers and the buffer cell against this library
icc2_shell> set_net_estimation_rule nimbus_bus -parameter "layer" \
    -horizontal_value "M3" -vertical_value "M6"
icc2_shell> set_net_estimation_rule nimbus_bus -parameter "buffer_spacing" \
    -value "500.000"
icc2_shell> set_net_estimation_rule nimbus_bus -parameter "register_spacing" \
    -value "1200.000"
icc2_shell> set_net_estimation_rule nimbus_bus -parameter "buffer" \
    -value $bufcell
icc2_shell> report_net_estimation_rules nimbus_bus

Other parameters exist: utilisation, derate, NDR, corner, capacitance, resistance. They are working knowledge. If you do not set a layer, the tool picks the middle of the current min and max routing layers. If you do not set a buffer, it chooses one. Unique rule names at the top of the hierarchy save you from a child block silently owning a different nimbus_bus.

Part 3 — Topology plans

A topology plan is the map. create_default_topology_plans builds a base plan for one bundle, or for every bundle if you name none. Each base plan has a start node, an end node, and an edge. If the endpoint sits inside a block, the end node is planted at the centre of that block. If the bundle already contains feedthroughs, nodes appear inside those rooms. Generated names follow TOPOLOGY_PLAN_<bundle_name>.

The flow picture sometimes writes the command in the singular. The command page, and every example that actually returns a collection, use the plural. New Tcl uses the plural. Confirm with man.

# Base plan for the teaching bundle, eating nimbus_bus
icc2_shell> create_default_topology_plans -net_estimation_rule nimbus_bus \
    [get_bundles nimbus_cpu_npu_bus]

You may also build a plan by hand with create_topology_plan, plant nodes with create_topology_node, and join them with create_topology_edge. Floating nodes that never joined an edge can be tied in with create_topology_connections -style fishbone, or chain, or star, or a compass style. Fishbone is the teaching automatic: each floating node joins the nearest spine edge.

Feedthrough and flyover are permissions on the plan, not decorations. -allow_feedthrough is none, select_on, select_off, or all. The same four words exist for flyover. Type pure, mixed, or any when you mean a feedthrough type. Do not leave “the bus can go through anything” as an accident.

The plan you just created becomes current. current_topology_plan with no arguments returns it. With a name, it sets it. report_topology_plans writes the NER, the nodes, the edges, the repeater count. Use -verbose when you are debugging a node you cannot see.

Part 4 — Check, refine, and feasibility

This is the tasting that belongs before the long walk. check_topology_plans -mode pre_optimization is a sanity check on the base plan. The flow picture labels it pre_check. That nickname is not a legal mode. The command page lists four tokens: pre_optimization, post_optimization, pre_implementation, post_implementation. New Tcl uses those. Confirm with man.

icc2_shell> check_topology_plans -mode pre_optimization

When the check speaks, it speaks in DPPA numbers. DPPA-543: a node’s pins sit on a layer the NER does not include. DPPA-541: two nodes overlap and interleave pins on the same layer. DPPA-499: an edge overlaps a cell it is not allowed to feed through or fly over. DPPA-498: an edge is too close to a cell boundary. DPPA-497: two edges collide. DPPA-496 is the cousin of 543, still a layer-versus-NER fight. DPPA-495 warns that the bundle is wide and may need extra repeaters. DPPA-494 notes a pin order that disagrees with the bundle order. Read them. Revise the plan. Then optimize.

Feasibility is a different question: can this netlist path be implemented by this topology path? Extra feedthrough rooms on the map are allowed. A netlist room that the map skipped is not. The command is check_topology_feasibility, with an i. A nearby sentence in some notes drops that i. Do not copy the missing letter. Some examples also print a double prompt. Type the command once.

# Topology may add feedthrough F. It may not skip netlist block E
icc2_shell> check_topology_feasibility -plan T1 -from T1/A0 -to T1/Z0

If the map skipped E, the tool tells you to create a node that matches E/out and connect it. That is a missing station, not a routing DRC.

refine_topology_plans is the kindness for a long walk. Instead of planting every feedthrough node by hand, you refine. New nodes appear where Manhattan edge segments cut block boundaries — but only if the edge already has a layer-shape attribute in Manhattan style. Otherwise the command quietly creates nothing. Return 1 still happened. Inspect the node count.

Part 5 — Optimize and repeaters

Now the crew walks the map. optimize_topology_plans derives a Manhattan route, adds repeaters and sequential elements according to the NER, and, if the endpoint is a block or a feedthrough room, creates pins on that block. Return 1 means the walk finished. Then you taste with -mode post_optimization.

icc2_shell> optimize_topology_plans [get_topology_plans TOPOLOGY_PLAN_nimbus_cpu_npu_bus]
icc2_shell> check_topology_plans -mode post_optimization \
    [get_topology_plans TOPOLOGY_PLAN_nimbus_cpu_npu_bus]

-repeaters_only plants virtual register and buffer locations without adding nodes or edges. -no_route creates feedthroughs and pins from a plan that already has a complete routing topology. Neither is a waiver of the check.

Repeater optimization runs in two passes: honour the spacing, then legalise and insert extras where the first pass left a gap. By default the command honours physical and logical locations of repeaters that already exist. To stop that, set plan.interconnection.enforce_repeaters_hiers to false and read it back with report_app_options. Do not memorise a hidden default.

If part of a bundle’s hierarchy should be ignored — a room whose netlist you do not want to constrain this walk — set the user attribute stop_hierarchy on the bundle. create_default_topology_plans honours it. So does optimize, once the attribute is there.

icc2_shell> set_attribute [get_bundles nimbus_cpu_npu_bus] stop_hierarchy {u_isp}

Suggested repeaters on a plan are not yet cells. implement_topology_repeaters -topology_plans ... places existing registers first, then inserts buffers or inverter pairs. If register placement fails, buffers are not inserted. Default name prefixes are cir_cell and cir_net. remove_implement_topology_repeaters takes them back out. report_topology_plan_registers -type unimplemented is the default; -type all includes what is already bound. Unimplemented repeaters still have no objects attribute. That warning is information, not a crash.

Part 6 — Groups, propagate, write-out

Large chips cut the work into topology groups. create_topology_group -name ... -plans ... makes a named set. Plans with no group land in DEFAULT_TOPOLOGY_GROUP. current_topology_group reads or sets the current group. remove_topology_groups removes groups; -all is the wide broom. Removing a group does not, by itself, remove the plans unless you ask it to.

The two NPU copies share one multiply instantiated block drawing. Build the plan on the instance you can see, then propagate_topology_plans across the other copies in the current design. -no_overwrite keeps a destination that already has a plan. Without it, the guest is overwritten.

icc2_shell> propagate_topology_plans [get_topology_plans TOPOLOGY_PLAN_nimbus_cpu_npu_bus]

To rebuild the same maps in a cousin design, write them out. write_topology_plans -filename nimbus_topology.tcl emits Tcl. -log also writes the console. -include_objects adds bundle and supernet creation. -pins_locations writes side-node constraints with start and end offsets, so a similar chip that does not yet have pins can still receive the map. -current_block keeps the write inside the block you are in. The generated script will remove_topology_plans a name before recreating it. That is deliberate, not vandalism.

icc2_shell> write_topology_plans -pins_locations -include_objects \
    -filename nimbus_topology.tcl

Part 7 — Branching, ripping, bidirectional

Branching is the honest fan-out: every net in the bundle shares one driver block and the same load blocks. Ripping is the almost: most bits share the loads, one bit peels off. For ripping, build the plan so every load block — even the odd bit’s private load — has its own node, the driver has a node, and the graph is connected. Optimize will then group pins, honour spacing, associate pins with the correct node, and order them by bit order.

Bidirectional bundles interleave opposite directions to reduce crosstalk. All nets in that bundle must be supernets if you will run the topology commands on them. They must connect the same two leaf blocks, and they must keep order from driver to load or load to driver. Create the supernets, then bundle opposite directions together.

These three shapes are working knowledge you can name in an interview. They are not the first Nimbus-8 cook. The first cook is a one-way 128-bit walk through the leftover channel, checked, then optimized.

Part 8 — Routing corridors and global routes

A topology plan is a map. A routing corridor is a fence you draw on the floorplan so global routing prefers that strip. During global routing, assigned nets are guided through the corridor. The corridor is not exclusive: other nets may still enter. You may set min and max layers, or inherit the design defaults. Optimization does not legalise cells inside a corridor.

Complete means the corridor encloses every pin of the assigned nets. Partial means at least one of those pins sits outside. Partial is legal. It is also how a report later says Shapes Cover Pins and Ports: no while the command still returned 1.

# Teaching rectangle in the leftover channel. Measure it on the floorplan
icc2_shell> create_routing_corridor -name nimbus_cpu_npu_corr \
    -boundary {{1760 1860} {2200 2560}} \
    -min_layer_name M3 -max_layer_name M6 \
    -object [get_nets cpu_npu_data*]
icc2_shell> report_routing_corridors [get_routing_corridors nimbus_cpu_npu_corr]

Those coordinates are a teaching box in micrometres. Confirm they sit in the hatched glue, not inside CPU_CLUSTER. The syntax line for -end_endcap sometimes grows a stray letter on the page. Do not type it. Endcaps are flush, half_width, or full_width.

You can add nets with add_to_routing_corridor, grow the shape with create_routing_corridor_shape, take nets out with remove_from_routing_corridor, and cut a piece with remove_routing_corridor_shapes. get_routing_corridors returns the collection.

Then globally route only those nets:

icc2_shell> route_group -global_planning true -nets [get_nets \
    -of_object [get_routing_corridors nimbus_cpu_npu_corr]]

-global_planning true makes the router virtually flat and hierarchy-aware: it will connect to pins inside child blocks, honour their blockages and preroutes, and can create pins on the next level down. Combined with -stop_after_global_route true it skips track assignment and detail routing. You must name the nets, or -all_clock_nets, or a file; -nets and -all_clock_nets are mutually exclusive. This command is for critical nets before signal routing. After signal routing, the repair tool is route_eco.

If the corridor is partial, set route.global.connect_pins_outside_routing_corridor to true so the router may reach the pins that sit outside. Read the option back. Complete corridors do not need that gift.

Part 9 — Repeaters on the route and push-down

After the planned nets have a global route, you may insert repeaters on that route with add_buffer_on_route. That is a different insertion from topology-plan repeaters. It happens on the route, before objects are pushed into blocks and pins are punched.

# Confirm the lib_cell. Teaching distance 150 um
icc2_shell> add_buffer_on_route \
    -allow_insertion_over_cell [get_cells {u_cpu_cluster u_npu_core_0}] \
    -repeater_distance 150 -lib_cell $bufcell \
    [get_nets cpu_npu_data*]

The command detects inverter versus buffer from the library cell. It respects placement blockages and macros by default. -allow_insertion_over_cell is how you permit sitting on named blocks. -repeater_distance and -repeater_distance_length_ratio are mutually exclusive ways to space. You may scale by layer or by width. You may snap to sites. You may use it on incomplete routes. Many more options exist; this chapter does not invent them. See man.

Insertion is not legalisation. legalize_placement at top and in the blocks comes next. A net that changed needs route_eco to be whole again.

Then push. push_down_objects pushes top-level objects into blocks: nets, routes, vias, corridors, blockages, rows, and more. The object collection is required. To punch feedthroughs on a net:

icc2_shell> create_pin_constraint -type individual \
    -nets [get_nets cpu_npu_data*] -allow_feedthroughs true
icc2_shell> check_mib_alignment -cell_row -wire_tracks
icc2_shell> push_down_objects [get_nets cpu_npu_data*]
icc2_shell> push_down_objects [get_cells eco_*]

-type is required: individual or bundle. Feedthroughs default to whatever you do not say; say true when you mean them. For the two NPU copies, alignment against rows and tracks is optional in the flow and mandatory in judgement. MIB-203 names a track offset disagreement. That is not a topology-plan error. It is a later fight you want to see before you push.

Part 10 — Working knowledge

Name these without dumping flags. Shield placement on a default plan: outside, interleave, double_interleave, half_interleave. Segmenting an edge into pure H and V after refine or optimize: segmentize_topology_edge. What-if on layers: point the plan at a different NER and reoptimize. Clock trunks: Chapter 12. Full pin assignment: later. Do not drag those chapters backwards into this cook.

Inputs, outputs, and readiness

Preflight checklist

• Leftover channel is the measured 2.091 mm² = 2,091,000 µm², not a feeling, and you can point at it on the die.
• Teaching bus layers are M3 horizontal and M6 vertical. They are not the M4/M5 mesh.
• Every pin you are about to name came from get_pins, not from memory.
• The two NPU copies are one MIB reference, NPU_CORE, instances u_npu_core_0 and u_npu_core_1.

Guided tool workflow

One continuous worked example

Nimbus-8, still. Core 3.20 mm × 3.20 mm = 10.24 mm² = 10,240,000 µm². Channel 2.091 mm² = 2,091,000 µm². Teaching bus: 128 bits, CPU cluster to u_npu_core_0, then propagate onto u_npu_core_1. NER nimbus_bus on M3/M6, buffer spacing 500 µm, register spacing 1,200 µm. Mesh on M4/M5 stays where Chapter 10 left it.

Query pins. Create one teaching supernet, then a bundle of the family. Write the NER and report it. Create the default plan for that bundle. Report the plan: you want a start node in the CPU room, an end node in the NPU room, and an edge that walks the leftover channel rather than diagonally through the ISP sofa. Pre-check. If DPPA-543 fires, the pin layer is not in the NER — fix the rule or the pin layer, do not ignore the number. Feasibility with an extra feedthrough through glue is a match. Feasibility that skips a netlist room is a mismatch. Optimize. Post-check. Propagate. Alignment. Only then a corridor in the measured glue, a route_group of those nets, buffers on the route, legalise, ECO, push-down.

Quiet success in this story is optimize_topology_plans returning 1 while the cover-pins line is still no, or while DPPA-495 is still warning that 128 bits are wide. Read the line. Do not argue with the heartbeat.

Failure modes and debugging

Hands-on mini lab — Capella-6

Capella-6 is a new design, not Nimbus-8. The core is a square 700 µm = 0.700 mm on each side, so an area of 0.49 mm² = 490,000 µm². Two committed blocks sit left and right with a leftover strip between them. The teaching bus is 32 bits. Use NER layers M3 horizontal / M4 vertical — on this small lab the power mesh is not the Nimbus-8 mesh, so M4 is free here. Buffer spacing 200 µm.

Steps.

1. Query a driver pin on the left block and a load pin on the right. Create a supernet. Bundle with -minimum_nets 32 if you use patterns, because 32 is above the default eight and you still want only this family.
2. Write NER capella_bus with layer M3/M4, buffer_spacing 200, a buffer cell you queried. Report the rule.
3. Create the default topology plan for that bundle. Report nodes and edges.
4. Run check_topology_plans -mode pre_optimization. Do not type pre_check.
5. Run feasibility from the start node to the end node.
6. Optimize. Post-check. Read whether any DPPA message remains.
7. Draw a corridor in the leftover strip. Report whether shapes cover pins. If no, enlarge or set the partial option. Globally route those nets with -global_planning true.

Expected observations. The plan name follows TOPOLOGY_PLAN_<bundle>. Pre-check and post-check are different modes. A 32-bit bundle is wide enough for DPPA-495 to be worth reading. Return 1 after optimize can coexist with a cover-pins line of no.

Verification checklist. Pins were queried; NER layers are M3/M4; spacing is 200 µm; mode tokens match the command page; cover-pins was read; no conclusion rests only on return 1.

Stretch. Add a fake third room on the netlist path and omit it from the topology path. Record the feasibility message. Add the missing node. Check again.

Interview preparation

Chapter close

Sign-off checklist for this planning stage

1. Driver and load pins were queried, not invented.
2. Supernets exist; the bundle is not empty; pattern thresholds were honest.
3. NER nimbus_bus is M3/M6 (or the lab’s stated pair), reported back, buffer cell confirmed.
4. Default topology plan used the plural command and a named bundle.
5. Pre-optimization used a command-page mode token, not pre_check.
6. Feasibility covers every netlist room; extra feedthroughs are explained.
7. Optimize return 1 was followed by post-optimization and a read of DPPA messages.
8. MIB copies were propagated on purpose; alignment was checked before push-down.
9. Any corridor’s cover-pins line was read; partial was a decision, not an accident.
10. Clock trunks were not mixed into this script.

Key-concept flashcards

Compact glossary

Five-question self-check

Regulus-3 has a core that is a square 1,000 µm = 1.000 mm on each side, so an area of 1.00 mm² = 1,000,000 µm². Its teaching bus is 64 bits. NER buffer spacing is 250 µm.

1. You have a driver pin and two load pins on the same physical hierarchy. Which create_supernet shape do you use, and why is -reuse illegal on that call?
2. A flow note says check_topology_plans -mode pre_check. What do you type instead, and which two further modes exist?
3. Netlist path is A → E → Z. Topology path is A → F → Z. Is that feasible? What do you add?
4. A corridor creates successfully. The report says Shapes Cover Pins and Ports: no. Name the corridor type and the two honest repairs.
5. Regulus-3 uses 250 µm buffer spacing across a 1,000 µm core. What is the first-order repeater count along a straight 1,000 µm edge, and why is it not a strap count?

Answers.

1. Use -start and -stop with the driver in start and the two loads in stop. -reuse may be specified only with a pin-or-port anchor, not with start/stop. Query the pins first.

2. Type -mode pre_optimization. The other documented modes are post_optimization, pre_implementation, and post_implementation. Confirm with man. Do not invent pre_check.

3. Not feasible: E is on the netlist and missing on the map. Extra F would have been legal in addition to E, not instead of E. Add a node covering E’s pin and connect it, then check again.

4. Partial. Enlarge the boundary until every assigned pin sits inside (complete), or set route.global.connect_pins_outside_routing_corridor to true and read it back. Return 1 did not cover the pins.

5. 1,000 / 250 = 4 spacings along a straight edge as first-order arithmetic, so a handful of repeaters, not 160 straps. Repeater spacing is a NER length along a bus. Strap count was Chapter 10’s mesh pitch. Do not copy 3,200 / 20 into this answer.

Why Chapter 12 follows

The leftover channel now has a bus map, and the mesh still holds power. What the chip still lacks is a coarse clock distribution from source to trunk endpoints that pin placement can honour. That is clock trunk planning. It is not a tail on optimize_topology_plans. This chapter ends with buses. The next begins at the clock port.