CHAPTER THIRTEEN

Pin Assignment: A Door Is Not a Route

By the end of this chapter you will know what a pin is, what a port is, and what a feedthrough visit is. You will fence the sides a room may use. You will keep a bus together as a bundle. You will check the design before you place, then place, then check again. And you will treat a returned place_pins as a heartbeat, not as a finished pin plan.

Why this chapter matters in a real project

Think of a chip as a city of rooms. Power is already in the streets from Chapter 10. The data bus already has a map from Chapter 11. The clock already has a coarse spine from Chapter 12. What the city still lacks is an agreed set of doors. A pin is a door. The router cannot honour a map if the door sits on the wrong wall, on the wrong layer, or on a wall you promised to a clock.

Sit with Nimbus-8 the morning after Chapter 12. The leftover channel is still 2.091 mm² = 2,091,000 µm². The 128-bit CPU–NPU bus still has a map through that leftover. clk_cpu still ticks at 1.60 GHz = 625 ps, and its spine still ends at an estimated 0.200 ns = 200 ps. Those clock pins stay where you put them. Today you assign every other door the router will use.

If you skip this chapter, two expensive things happen. Either the placer dumps a 128-bit bus onto the clock wall, or two NPU copies disagree about which pin is which. Multiply instantiated block, then MIB: two copies of the same drawing. On Nimbus-8 those copies are u_npu_core_0 and u_npu_core_1, sharing NPU_CORE.

One more thing, because it will happen to you. You will type place_pins. It will return 1. That means the command finished. It does not mean every pin is on a legal side. It does not mean the bundle stayed together. It does not mean check_pin_placement is a report you would ship. Those are other commands.

Prerequisites

Chapter 12, because clock pins are already placed and must stay fixed. Chapter 11, because the leftover channel already holds a bus map and you must not park every pin through the ISP sofa. Chapter 10, because M4 and M5 already carry the 20 µm power mesh. Chapter 9, because blocks are shaped. Chapter 8, because a module is a name and a block is a physical room — pins sit on rooms, not on names.

The library is nimbus8.dlib. The top is NIMBUS8. Teaching pin, port, and net names in this book are stand-ins. Query them with get_pins, get_ports, and get_nets. Brace Tcl indexes.

How to read the numbers and the notation in this chapter

Read this table slowly. Every later command uses these words. If a word here is still fog, stop and read the row again before you type Tcl.

Learning objectives

After this chapter you will be able to:

1. Say what a pin, a port, a terminal, a side, a bundle, and a feedthrough are, in plain words.
2. Number sides from 1, clockwise, and put the CPU leftover on side 3.
3. Create a pin blockage, including the feedthrough-only flavour.
4. Set block pin constraints, name the retirement conflict, and read them back.
5. Write individual and bundle constraints with create_pin_constraint, and name the other family.
6. Load a pin-constraint file with four sections, and write one back with a required -file_name.
7. Run check_pre_pin_placement before place_pins, and read DPPA-441 as a direction clash.
8. Place pins with the documented switches, then check, report, and estimate length.
9. Keep MIB copies honest with check_mib_for_pin_placement.
10. Leave budgeting for Chapter 14, and leave clock trunks in Chapter 12.

The beginner’s mental model

A loading dock is not the motorway

Hold a warehouse drawing that shows only the docks. The motorway that connects two warehouses is someone else’s drawing. A pin is a dock. The net is the truck. Chapter 11 already drew the motorway for the 128-bit bus. This chapter decides which dock the truck uses, on which wall, on which floor of metal.

The analogy stops being silicon quite quickly, and that is the point. A dock has a numbered wall. Side 1 is the leftmost lowest edge, then clockwise. A dock sits on a metal layer whose preferred direction must match that wall. Two copies of the same warehouse must have matching docks. A cheerful return value means the placer finished. Tasting is check_pin_placement.

The precise engineering model

The database already has shaped blocks, a leftover channel, a compiled power grid, a bus map, and a clock spine. Pin assignment adds legal doors on that geometry. You optionally draw a no-parking zone. You set rules for a whole room. You set rules for one pin or one bundle. You may load a constraint file that names walks and visits. You check whether those rules even make sense. Then you place. Then you check again.

Two families of Tcl exist for the same job, and they are not a style choice. The flow picture writes create_pin_constraint for individual and bundle rules, and set_block_pin_constraints for the room. The place_pins command page also lists set_individual_pin_constraints, set_bundle_pin_constraints, and create_block_pin_constraint. The block command page says set_block_pin_constraints will retire, and names create_block_pin_constraint as the successor. New Tcl in this book uses the flow cook: set_block_pin_constraints and create_pin_constraint. Name the other family. Confirm with man.

The practical loop is kind to beginners. Fix clock pins. Fence sides. Bundle the bus. Pre-check. Place. Check. Write the map back. Four small walks are easier to debug than one giant one.

Concepts built from first principles

Part 1 — What a pin actually is

Do not start with a command. Start with the thing the command is trying to build. If you cannot point at a door, a wall, a layer, and a visit on a sketch, the Tcl will only hide the fog.

Pin, port, terminal, feedthrough

A pin is a door on a block. A net uses that door to enter or leave the room. Query it with get_pins. A port is a door at the top of the design you are sitting in. Query it with get_ports. A terminal is the metal shape of that door: a rectangle on a layer, snapped to a wire track. Query it with get_terminals.

A feedthrough is a visit. The net walks through a room that is not the destination. The tool may split the original net, create new ports, and change the netlist. That is not a small side effect. Say the word visit out loud before you allow it.

Teaching names in this book are stand-ins. On a real netlist you ask the design. You do not type a name from memory.

Sides, clockwise from 1

Every edge of a room has a number. Side 1 is the leftmost lowest edge. Then you walk clockwise. On a simple rectangle that is: 1 left, 2 top, 3 right, 4 bottom. You cannot specify 0. On Nimbus-8 the leftover channel faces the right edge of CPU_CLUSTER. That is side 3. The matching NPU doors face left. That is side 1 of each copy.

A nearby example writes -side 3, no s. The command pages write -sides. New Tcl uses -sides. Confirm with man. -sides and -exclude_sides are mutually exclusive. An empty list resets.

Layers this chapter may use

A pin sits on a metal layer. That layer has a preferred routing direction. A horizontal layer wants a vertical edge — sides 1 or 3. A vertical layer wants a horizontal edge — sides 2 or 4. If you fence a horizontal layer onto the top and bottom, the pre-check will tell you. That message is DPPA-441. It is a constraint conflict, not a router bug.

On Nimbus-8 the teaching bus from Chapter 11 lives on M3 horizontal and M6 vertical. The power mesh from Chapter 10 still owns M4 vertical and M5 horizontal at a 20 µm pitch. You do not steal M4 or M5 because they look fat. You query get_layers. You do not invent METAL3 if the library says M3.

Do not confuse these

Part 2 — Pin blockages

A pin blockage is a region where pins must not sit. Draw it before you place. The boundary can be a rectangle, a polygon, or a collection of objects with physical geometry. If you name pins, nets, or ports, the list must be one type — not a mix. If you name none, every pin avoids the region.

# Rectangle. All layers. Every pin avoids PB_1
icc2_shell> create_pin_blockage -boundary {{100 100} {200 200}} -name PB_1

# Rectilinear region, only M1 and M2
icc2_shell> create_pin_blockage -boundary {{0 0} {2000 0} \
    {2000 2000} {1000 2000} {1000 1000} {0 1000}} -layers {M1 M2}

# Homogeneous pin list. Teaching names: query first
icc2_shell> set pins [get_pins -physical_context cell1/pin*]
icc2_shell> create_pin_blockage -boundary {{100 100} {200 200}} $pins

Remove with remove_pin_blockages. Report with report_pin_blockages. A pin guide or a routing corridor is the opposite idea: a region pins should stay inside. Do not mix the two in your head.

Part 3 — Precedence

Several rules can claim the same pin. The tool does not average them. It stacks them.

1. Topological map and feedthrough control in the constraint file override global feedthrough settings.
2. Individual pin constraints beat bundle pin constraints.
3. Bundle pin constraints beat nondefault routing rules.
4. Nondefault routing rules beat block pin constraints.
5. More restrictive beats less restrictive. An exact location beats a pin guide.
6. Among several constraints of the same kind, the last one specified wins.

When an individual side, offset, layer, or order fights a bundle, place_pins ignores the bundle for those nets and still tries to keep the other bundle pins together. When width, length, or spacing fight, the tool honours both if it can. Hard constraints skip DRC. Feedthrough-only blockages sit above other pin constraints on conflict.

Part 4 — Block pin constraints

Block pin constraints are the floor of the stack. They apply to all pins of a room unless a higher rule takes over. The flow cook is set_block_pin_constraints. Report with report_block_pin_constraints. Remove with remove_block_pin_constraints, then set again.

# CPU leftover faces side 3. Query layers. Visits off unless you mean them
icc2_shell> set_block_pin_constraints \
    -cells [get_cells u_cpu_cluster] \
    -sides {3} \
    -allowed_layers [get_layers {M3 M6}] \
    -allow_feedthroughs false \
    -pin_spacing 1 \
    -corner_keepout_num_tracks 5

On Nimbus-8 you also fence the NPU copies to side 1, and you keep ISP closed to visits so the bus cannot punch the sofa. Read the constraints back. Empty is not a recipe.

icc2_shell> report_block_pin_constraints

Part 5 — Individual pin constraints

After the room rules, you may constrain one pin, one port, or one net. Individual rules beat the bundle and beat the room. The flow cook is create_pin_constraint -type individual. You must give -type individual and at least one of -pins, -ports, or -nets.

The other family is set_individual_pin_constraints. place_pins honours it. Layer switch there is -allowed_layers, not -layers. New Tcl uses the flow cook. Name both. Confirm with man.

To clear the flow-cook objects, the flow uses remove_pin_constraints [get_pin_constraints -filter {pin_constraint_type=="individual"}]. That command exists. The other family clears with remove_individual_pin_constraints. Do not mix the two as if they were one broom.

# Teaching pin: query first. Last specified wins if you set twice
icc2_shell> create_pin_constraint -type individual \
    -pins [get_pins {u_cpu_cluster/rstn}] \
    -sides {4} \
    -width {{M3 3} {M5 5}} -length {{M3 3} {M5 5}}

# Offset as a percentage of side 3. Command page: -sides, not -side
icc2_shell> create_pin_constraint -type individual \
    -layers [get_layers {M2 M3}] \
    -nets [get_nets clk] \
    -offset {10% 40%} -sides {3}

Report the flow-cook objects with report_pin_constraints. The pre-check narrative also names report_individual_pin_constraints. That command exists too. Use the report that matches the family you set.

Part 6 — Bundles

A bundle is a named ribbon of nets. The placer tries to keep those doors together on one edge, on one layer, in an order you can defend. A 128-bit bus that scatters around a room becomes a knot.

# Teaching names. Query the nets. Brace indexes
icc2_shell> create_bundle -name cpu_npu_data \
    [get_nets {cpu_npu_data[127:0]}]
icc2_shell> report_bundles [get_bundles cpu_npu_data]

Automatic bundles from a prefix:

icc2_shell> create_bundles_from_patterns -net_name_prefix cpu_npu_data

Omit the prefix and the command looks for bus index patterns [i], (i), <i>, _i, :i, and {i}. Limit those with -no_braces, -no_brackets, -no_angle_brackets, -no_underlines, -no_colons, or -no_parentheses. Order with -net_order ascending|descending. Size with -minimum_nets and -maximum_nets.

Add or remove nets with add_to_bundle and remove_from_bundle. Collect with get_bundles. Delete with remove_bundles. You may also bundle supernets from Chapter 11. A bundle is not a supernet. Do not mix the words.

Then constrain the ribbon. The flow cook is create_pin_constraint -type bundle. A nearby example writes keep_pins_together true without the dash. The command page writes -keep_pins_together. New Tcl keeps the dash.

# Dash on the switch. Query the bundle
icc2_shell> create_pin_constraint -type bundle \
    -bundles [get_bundles cpu_npu_data] \
    -keep_pins_together true \
    -layers [get_layers {M3 M6}]

The other family is set_bundle_pin_constraints. check_pin_placement -keep_pins_together talks about that family. Name both.

You can split a wide bus into two ribbons on purpose. Bits 0–127 walk through one room. Bits 128–255 walk through another. That is two bundles, two constraints, two walks — not one giant ribbon you hope will behave.

Priority among ribbons: smaller pin_placement_priority_id is placed first. Bundle nets beat non-bundle nets when bundle placement is enabled.

icc2_shell> set_attribute [get_bundles cpu_npu_data] pin_placement_priority_id 1

Part 7 — The constraint file

Tcl is not the only way. A pin-constraint file can name walks, visits, physical locations, per-edge spacing, and room rules. Load it with read_pin_constraints -file_name. Write it with write_pin_constraints, where -file_name is required.

Supported section headers, each ended with a matching end …;:

• start topological map; — the walk through rooms.
• start feedthrough control; — which rooms may be visited. Later statements override earlier ones for the same net.
• start physical pin constraints; — side, layer, offset, off-edge, location. Last record wins on an MIB port.
• start pin spacing control; — per reference, per sides, per layer track spacing. Unspecified layers on those sides are not used.
• start block pin constraints; — the same floor you can set in Tcl.

Comments begin with #. Curly brackets group objects. A semicolon ends a record. Keywords are case-insensitive; reference names and layer names are not.

# Teaching walk. Names are stand-ins. Query cells and nets
start topological map;
{Nets cpu_npu_data*}
{{Cell u_cpu_cluster} {Cell u_npu_core_0}}
{{Cell u_cpu_cluster} {Cell u_npu_core_1}};
end topological map;

A topological record can also name sides, offsets, and layers on each cell. Partial paths are allowed. Mixed feedthroughs — allowed in some rooms, banned in others — live in the feedthrough-control section as {Feedthrough …} and {NoFeedthrough …}.

The GUI can draw the same walk. The flow names create_topological_constraint (singular) for that Tcl. The place_pins page lists create_topological_constraints (plural). New Tcl: confirm with man which token exists on the build in the room. Retrieve with get_topological_constraints. Report with report_topological_constraints -all. Remove with remove_topological_constraints.

Part 8 — Before you place

If the design has MIB copies or existing visits, you may global-route first, then place from that route.

# Virtual-flat: top and children, or top-and-interface only
icc2_shell> route_global -floorplan true \
    -virtual_flat all_routing
icc2_shell> place_pins -use_existing_routing

-virtual_flat top_and_interface_routing_only routes the top and the nets that touch children, including interface and feedthrough nets. -use_existing_routing cannot combine with -pins or with -nets_to_exclude_from_routing. Those routes are removed after place. If no route exists for a net, the door may not be optimal, and the command will not invent a flyline either.

A channel congestion map, before place, uses create_channel_congestion_map -channel_width_threshold. Channels wider than the threshold are ignored. The command runs a global route first. View it in the GUI as Channel Congestion. There is also a what-if panel. Teaching: look, then constrain. Do not place into a channel you already know is full.

Then the named pre-check. Either:

icc2_shell> check_pre_pin_placement
icc2_shell> check_design -checks {dp_pre_block_shaping \
    dp_pre_macro_placement dp_pre_pin_placement}

Also useful before place: report_placement, check_mib_alignment from Chapter 11, check_mib_for_pin_placement, and the report commands for each constraint family.

Part 9 — place_pins

After the rules, place. The command global-routes, then snaps doors to wire tracks. It does not use reserved tracks. Top ports use top tracks. Block pins use tracks inside that block, or top tracks if the child has none.

# Heartbeat is 1. Taste is the next part
icc2_shell> set_host_options -max_cores 4
icc2_shell> place_pins

If constraints are too tight and not hard, the placer relaxes in a documented order: spacing versus offset depending on whether a range exists, then edge abutment, then offset, layer, and spacing in further passes. Hard constraints skip their relaxation. That is why a hard location inside a blockage still sits there.

Application options steer the same command. Read them back with report_app_options. Do not memorise a hidden default.

Other documented options exist — black-box style, colour span rules, inout-net visits, bus naming, path-based placement. Do not invent a sixth one. Read the option you mean.

Part 10 — Incremental, MIB sharing, and alignment

place_pins already removes nonfixed terminals each run. To force a clean edge, remove_terminals on the pins of that room. Avoid remove_pins unless you mean to disconnect nets. That command changes the netlist.

Hard bundles first, then fix, then the next ribbon:

# Teaching: difficult ribbon first. Query bundles
icc2_shell> set_block_pin_constraints -allow_feedthroughs true
icc2_shell> create_bundle -name B1 [get_nets {Data[0] Data[1] Data[2] Data[3]}]
icc2_shell> create_bundle -name B2 [get_nets {Data[4] Data[5] Data[6] Data[7]}]
icc2_shell> set_bundle_pin_constraints -keep_pins_together true
icc2_shell> place_pins -nets [get_nets -of_objects [get_bundles {B1}]]
icc2_shell> set_fixed_objects [get_pins -filter "is_hierarchical==true" \
    -of_objects [get_nets -segments [get_nets \
    -of_objects [get_bundles {B1}]]]]
icc2_shell> place_pins -nets [get_nets -of_objects [get_bundles {B2}]]

Before an incremental pass that should be free to move, remove_feedthroughs. Then optionally set plan.pins.incremental true. Clock pins from Chapter 12 belong in the fixed list before the 128-bit bus is placed.

On MIB copies, visits can explode. Set feedthrough_sharing_matching_id on nets or on bundles, not both. Same id means the tool tries to share. Default is 0 for every net. Setting two nets to different ids is how you stop them sharing.

Alignment after place is a different command. align_block_pins moves the alignee to the anchor. Two-pin nets only. Immediate sibling, nearest child, or nearest parent. No obstacles between the rooms. It does not honour side, layer, or offset constraints — place_pins does.

icc2_shell> align_block_pins -anchor u_cpu_cluster -alignee u_npu_core_0

It will not move a PG net, a multi-fanout net, a hard-macro alignee, a multi-terminal pin, or a fixed alignee pin. The report lists the skips. Read it.

Part 11 — Checking after place

Now taste. check_pin_placement has many switches. Teaching first pass:

icc2_shell> check_pin_placement -pin_spacing true -layers true
icc2_shell> check_feedthroughs -unused_feedthroughs \
    -reused_feedthroughs -net_constraints -topo_constraints
icc2_shell> check_mib_for_pin_placement -swapped_connections \
    -asymmetric_connections -top_level_terminal_locations
icc2_shell> report_pin_placement > pin_placement.rpt
icc2_shell> report_feedthroughs -reporting_style net_based

report_feedthroughs -reporting_style is required. Values are net_based or block_based. UG mentions -format {layer side offset cell} on the pin report. The command page lists -format {layer side offset}. New Tcl uses the command-page three tokens. Confirm with man.

More switches exist: blockage, guide, corridor, mask colour, size, stacking, wire track, wide track, synthesized abut pins, single-pin, technology spacing. Do not invent one. Name the one you ran.

check_feedthroughs teaching switches: -unused_feedthroughs, -reused_feedthroughs (MIB), -net_constraints, -topo_constraints, -redundant (almost mutex with the others), -include_buffered, -self, -cells, -alignment with -alignment_tolerance_distance. Unused on one MIB copy while another copy needs the visit is a classic MIB trap. That is why unused is a check, not an insult.

Part 12 — Write back, shadow ECO, and estimated length

Write what you have so the next session can honour it.

icc2_shell> write_pin_constraints -from_existing_pins \
    -file_name pin_constraints.map \
    -topological_map {side offset offset_range 5 layer layer_range 1}

Visits created by place_pins or push_down_objects set is_shadow true on the new objects. Replay them with write_shadow_eco.

icc2_shell> write_shadow_eco -command_style icc2 \
    -output feedthroughs.tcl

-command_style is icc2 or dc. -reporting_style is design_based (one script) or block_based (one script per block). To keep only recent rounds, set plan.pins.enable_feedthrough_timestamps true at the start of the session, then -latest_rounds {1 2} where 1 is the most recent place_pins or push_down_objects.

Estimated length after place is get_estimated_wirelength. The section title nearby says “Reporting Estimated Wire Length.” The command is not report_estimated_wire_length. It builds a virtual route across hierarchies. set_editability limits which hierarchies count. The number is an estimate, not signoff.

icc2_shell> get_estimated_wirelength
icc2_shell> get_estimated_wirelength -nets [get_nets {din[0] dout[0]}]

Inputs, outputs, and readiness

Preflight: blocks shaped, clock pins fixed, MIB copies identified, layers queried, leftover-facing sides said out loud (CPU 3, NPU 1), visits on or off said out loud, pre-check empty or explained.

Guided tool workflow

Validation gates: DPPA-441/458 empty or explained; spacing and layer checks clean or owned; MIB copies not swapped; estimated length labelled as an estimate.

One continuous worked example

Nimbus-8. Library nimbus8.dlib. Top NIMBUS8. Leftover 2.091 mm² = 2,091,000 µm². Teaching bus M3/M6. Mesh M4/M5. Clock pins already placed.

# Teaching stand-ins. Query before you copy
icc2_shell> set_fixed_objects [get_pins \
    {u_cpu_cluster/clk u_npu_core_0/clk u_npu_core_1/clk}]

icc2_shell> set_block_pin_constraints \
    -cells [get_cells u_cpu_cluster] \
    -sides {3} \
    -allowed_layers [get_layers {M3 M6}] \
    -allow_feedthroughs false

icc2_shell> set_block_pin_constraints \
    -cells [get_cells {u_npu_core_0 u_npu_core_1}] \
    -sides {1} \
    -allowed_layers [get_layers {M3 M6}] \
    -allow_feedthroughs false

icc2_shell> set_block_pin_constraints \
    -cells [get_cells u_isp] \
    -allow_feedthroughs false

icc2_shell> create_bundle -name cpu_npu_data \
    [get_nets {cpu_npu_data[127:0]}]
icc2_shell> create_pin_constraint -type bundle \
    -bundles [get_bundles cpu_npu_data] \
    -keep_pins_together true \
    -layers [get_layers {M3 M6}]

icc2_shell> check_pre_pin_placement
icc2_shell> place_pins -nets [get_nets -of_objects [get_bundles cpu_npu_data]]
icc2_shell> check_pin_placement -pin_spacing true -layers true -alignment true
icc2_shell> check_mib_for_pin_placement -asymmetric_connections \
    -swapped_connections
icc2_shell> report_pin_placement -nets [get_nets -of_objects \
    [get_bundles cpu_npu_data]] > pin_placement.rpt
icc2_shell> write_pin_constraints -from_existing_pins \
    -file_name pin_constraints.map
icc2_shell> get_estimated_wirelength -nets [get_nets -of_objects \
    [get_bundles cpu_npu_data]]

Read return 1 as a heartbeat. Read DPPA as a sentence. If the NPU copies disagree, you skipped the MIB check, or you placed only one instance with -cells and hoped the drawing would invent the other door.

Failure modes and debugging

Hands-on mini lab — Mira-6

Mira-6 has a core that is a square 800 µm = 0.800 mm on each side, so an area of 0.640 mm² = 640,000 µm². Two blocks, one leftover strip between them. One 32-bit bus. No MIB. Teaching layers M3 and M6. Side 3 of block A faces block B.

1. Query layers, nets, and pins. Do not invent names from this page.
2. Fence block A to side 3 and block B to side 1. Visits off.
3. Create a bundle for the 32-bit bus. Keep pins together, with the dashed switch.
4. Run check_pre_pin_placement. Repair DPPA-441 if you fenced a horizontal layer onto top and bottom.
5. Place the bundle nets. Read return 1 as a heartbeat.
6. Check spacing, layers, and alignment. Write a constraint file with -file_name.

You are done when the pre-check is empty or explained, the ribbon sits on the facing walls, and the written file opens with a section you can point at.

Interview preparation

Chapter close

Sign-off checklist for this planning stage

1. You can point at pin, port, terminal, side, bundle, and feedthrough on a sketch.
2. Pins, ports, nets, and layers were queried, not invented.
3. Clock pins from Chapter 12 were fixed before this cook.
4. CPU leftover used side 3. NPU leftover used side 1. Side 0 was never typed.
5. M3/M6 hold the teaching bus doors. M4/M5 still hold the mesh.
6. Visits were true or false on purpose. ISP was not a corridor.
7. Keep-together used the dashed switch. Individual still beats a ribbon.
8. Pre-check used check_pre_pin_placement. DPPA-441/458 empty or explained.
9. place_pins return 1 was followed by spacing, layer, feedthrough, and MIB checks.
10. write_pin_constraints -file_name was written. Estimated length was labelled an estimate.
11. Budgeting was not mixed into this script.

Key-concept flashcards

Compact glossary

Five-question self-check

Castor-3 has a core that is a square 1,200 µm = 1.200 mm on each side, so an area of 1.44 mm² = 1,440,000 µm². Two copies of one reference. Teaching bus layers M3 and M6. Leftover faces side 3 of the parent and side 1 of each copy.

1. You fence M3 onto sides 2 and 4. Which pre-check message do you expect, and what is the repair?
2. A flow note says create_pin_constraint -type bundle keep_pins_together true. What do you type instead, and which other family does check_pin_placement -keep_pins_together talk about?
3. You set set_block_pin_constraints -excluded_sides {2} and the tool rejects it. Why, and which successor uses that spelling?
4. After place, Castor-3’s two copies disagree about a two-pin net. Which check and which DPPA number name that, and what larger check is it a subset of?
5. A colleague asks for report_estimated_wire_length on Castor-3. What command do you run, and what honesty label sits on the number?

Answers.

1. DPPA-441 from check_pre_pin_placement: horizontal M3 is incompatible with top and bottom sides. Fence M3 onto sides 1 and 3, or pick a vertical layer for 2 and 4. Query get_layers.

2. Type create_pin_constraint -type bundle -keep_pins_together true and name -bundles. The other family is set_bundle_pin_constraints. Confirm with man.

3. The flow cook uses -exclude_sides, not -excluded_sides. The successor create_block_pin_constraint uses -excluded_sides. Do not mix the families. Confirm with man.

4. check_mib_for_pin_placement -swapped_connections, DPPA-203. It is a subset of -asymmetric_connections (DPPA-205).

5. get_estimated_wirelength. It is a virtual-route estimate, not signoff, and not a budget. There is no report_estimated_wire_length on the command pages this chapter sat with.

Why Chapter 14 follows

The leftover channel now has a bus map, a clock spine, and a set of doors you checked. The mesh still holds power. What the chip still lacks is an agreed split of the remaining window on the clk_cpu wave among those rooms. That is timing budgeting. It is not a tail on place_pins. This chapter ends with pins. The next begins at slack.