Chip finishing and post-fill qualification

13.1 Stage purpose

Finishing adds four groups of objects. Filler cells fill the gaps between standard cells so that the power rails and the n-wells run without a break. End-cap and well-tap cells close the ends of the rows and tie the wells to the supply at a set distance. Decap cells add decoupling capacitance. Metal fill is a set of dummy metal shapes, and via fill the equivalent for cut layers. Both exist to make the density of each layer more even, which helps manufacturing.

Metal fill is useful and not free. The added metal increases the coupling capacitance to neighbouring signal wires, so each window of the layout trades a better density for a little more delay. Figure 18 shows this on one small region: before fill, the four windows hold between 8 and 14 percent metal; after fill they are closer together, and the ledger lists what that cost in shapes and in added capacitance. The numbers are illustrative.

Three different densities appear in the reports of this stage, and they are easy to confuse. Placement density is the share of row sites occupied by cells, and checkPlace and reportDensityMap report it. Metal density is the share of a window covered by metal on one routing layer, and verifyMetalDensity reports it. Cut density is the same idea for via layers, and verifyCutDensity reports it. A clean result for one says nothing about the others.

The order of the steps matters, and Figure 19 gives the sequence this chapter follows. A later step can invalidate an earlier check, which is why the loop on the right returns to the density and timing checks. The last card, H-10, covers the export of the finished database to stream, OASIS, DEF and a physical netlist, which happens after the loop has settled. Antenna repair is not a step in the figure. It reroutes metal, so close it before filler and fill where you can, and see card H-08 for the reruns if it happens late.

This chapter keeps four things apart. Tool completion means a command ran. Analysis coverage means the check looked at every layer, window and cell it needed to. Stage qualification means the evidence supports leaving chip finishing. Signoff is the final verification in the project signoff tools, which this chapter does not replace. An empty report is not a pass, and a fill run that finishes does not show that any density rule is met.

13.2 Entry prerequisites

13.3 Relevant files and analysis context

The inputs are the filler list, the tap and end-cap rules, the density rules, and the layer map that connects Innovus layer names to stream layer numbers for the fill data. The outputs are the filler and tap instances in the database, the fill data, and the report files that each card names.

Three settings are stored with the design and therefore change what a later run does: setFillerMode, set_metal_fill_signoff_mode and set_verify_drc_mode. The reference states that parameters given directly to addFiller apply to that run only and supersede setFillerMode. Thus, record the stored values with each report, because two runs with different stored values check different things.

Signoff fill is kept as a hierarchical fill database. The reference lists -auto_load_fills, -view_fills and -flatten for bringing it into the session, and describes flattening as the editable mode for DRC, density and timing. Confirm that the fill is loaded or attached before you read a density, DRC or trim result as complete. Whether each check sees fill that is not loaded is not verified here.

The timing views for the post-fill comparison are the same views used for post-route signoff preparation in Chapter 12. Use the same views, the same analysis mode and the same constraint set before and after fill, or the difference you measure is not the effect of fill.

13.4 Checks and command cards

13.4.1 Pre-stage checks

Before any filler is added, store four baselines. Each one makes a later number meaningful.

13.4.2 Post-stage checks

getFillerMode
addFiller -cell {<filler cells>} -prefix FILLER

checkFiller -file <f>

verifyWellTap -rule <um> -report <f>
reportDeCap -area <llx> <lly> <urx> <ury>

checkPlace <report_file>

get_metal_fill_signoff_mode
report_metal_fill -fill_area -file <f>

verifyMetalDensity -report <f>
verifyCutDensity -layer {<cut layers>} -report <f>

verify_drc -limit 0 -report <f>
verifyConnectivity -type all -report <f>

verify_antenna -report <f>

timeDesign -postRoute -outDir <dir> -prefix <prefix>

streamOut <name>.gds -mapFile <map>
defOut -floorplan -routing <name>.def
getStreamOutMode
setStreamOutMode -check_map_file true
streamOut <name>.gds -mapFile <map> -signoff_fill
streamOut <name>.oas -mapFile <map> -format oasis
saveNetlist <name>.v -includePhysicalInst -includePowerGround

13.5 Required reports, artefacts and how to read them

checkFiller                                              ## illustrative excerpt
*INFO: Total number of gaps found: 0

report_metal_fill -fill_area -file fill_area.rpt
Metal Fill Summary
<numFillShapes>=<fillArea>squm(<percentTotal>)
|floating         |total
------------------------------------------------------
M2| 1820= 24960.40 (100.00%)  | 1820= 24960.40
M3| 1764= 24102.15 (100.00%)  | 1764= 24102.15
M4| 1530= 21876.80 (100.00%)  | 1530= 21876.80
M5| 1105= 15432.55 (100.00%)  | 1105= 15432.55
------------------------------------------------------
sum| 6219= 86371.90 (100.00%) | 6219= 86371.90

The filler check reports zero gaps, which answers one question only: no site is missing a filler. It says nothing about the DRC state of those fillers, and the plain form does not check stack length, which needs -horizontal_max_length and -vertical_stack_max_length. In the fill summary, the floating column and the total column agree on every layer, so all fill is floating and none is connected to a net. That may be exactly what your project wants, since the reference notes that floating fill adds less capacitance than connected fill. Check the choice against the project record.

Next, compare the layers listed with the layers in your fill rule. This sample shows no fill on M1 or M6, which is correct only if the rule excludes them. Finally, add up the shapes: the sum row of 6,219 shapes equals the total of the four layers, so the report is internally consistent. Consistency is not density. The density result comes from card H-06. All numbers here are illustrative and are not from a tool run.

13.6 Healthy, suspicious and hard-stop examples

13.7 Debugging, corrective action and reruns

Fix finishing problems in the order of the chip-finish flow, because each later check depends on the earlier objects. A filler DRC violation comes first, since fill is computed around the filler. Next come density problems, then timing. A timing repair by trimming removes metal, so it can reopen a density problem, and the density check follows every trim.

13.7.1 What must not move after fill

Fill is generated against the metal that exists when it runs. After it, treat the following as frozen unless you declare an ECO and repeat the finishing sequence.

After a justified ECO, use addFiller -ecoMode true to remove fillers that overlap moved cells and refill the new gaps, and use add_metal_fill_signoff -incremental to update the fill. Then rerun every card in this chapter.

13.7.2 Worked example: fill that costs timing

Suppose the routed design had a setup WNS of +0.031 ns in the worst view before fill. After signoff fill, the same views give -0.012 ns. Every density and DRC card is clean, and H-09 is the first card to fail. Your project requires non-negative setup slack, so the status is HARD STOP. All values here are illustrative.

The failing endpoints all sit behind the net clk_a of Figure 18. The cause is known: fill shapes within a few tracks of that net add coupling capacitance. The reference describes this exact usage model for trimMetalFillNearNet: time the design before fill, add fill, time it again, and then trim the fill that made timing worse. The command takes a slack threshold, spacings on the same layer, the layer above and the layer below, and a minimum density that stops the trimming. It does not check DRC rules, so run H-07 after every trim, and add -createFillBlockage so that a later fill run does not refill the trimmed area.

In the figure, the trim removes four fill shapes from window W4 (the figure assumes -remove, which deletes whole shapes instead of cutting them back to the halo edge). The added coupling for that window falls from 2.08 to 1.12 fF in the ledger, and the window density drops from 17 to 15 percent. That drop is why the sequence ends with the density checks. A window that loses metal can fall below its minimum, and the minimum-density argument of the trim command is there to prevent that. The decision after the trim is therefore two decisions: H-09 passes when the slack is back inside budget, and H-06 must still pass on the trimmed layout. Rerun H-06, H-07 and H-09.