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CADENCE INNOVUS PLACE AND ROUTE SERIES

Cadence Innovus PnR Qualification Handbook

A stage by stage qualification handbook for Innovus place and route, in 16 chapters. Each chapter says what to check before you start the stage, what to run, how to read the report, and what counts as healthy, suspicious or a hard stop, so you can decide whether a run is fit to move on instead of only whether the tool finished.

ONE PAYMENT
Handbook PDF and Cheat Sheets PDF: 199 rupees · The 290-page handbook and the 83-page cheat sheet book, both in one download. Every chapter is free to read online.

Legacy commands are checked against the vendor reference. Nothing in the book claims a command was run on a live design. Example output is synthetic and thresholds are illustrative.

Setup

Tool, database and timing setup

Qualify the tool session, the imported design database and the timing environment before any physical work starts.

CHAPTER 01
Setup•Sanity and command sheets

Tool, project and session qualification

Before a single cell is placed, we need to know which tool, which interface, which inputs and which settings produced the numbers we are about to read.

  • Release and build
  • Active user interface
  • Log location and message history
  • Non-default settings
CHAPTER 02
Setup•Sanity and command sheets

Design import and database sanity

Import turns a netlist, a set of libraries and a technology description into one design database.

  • Load the design
  • Library binding and black boxes
  • Netlist structure and uniqueness
  • Design inventory against synthesis
Floorplan and power

Floorplan and power planning

Check the floorplan, macros, pins and power network that every later stage works inside.

CHAPTER 04
Floorplan and power•Sanity and command sheets

Floorplan, macro and pin qualification

The floorplan fixes the space every later stage works in.

  • Die and core geometry
  • Floorplan legality and utilisation
  • Macro placement and overlap
  • Pin assignment
CHAPTER 05
Floorplan and power•Sanity and command sheets

Power-planning qualification

Power planning builds the supply network that every later stage depends on and that every later stage must route around.

  • PG and tie-pin connection
  • Physical-only cells
  • Rings and stripes
  • Followpins and macro pin connection
Placement

Placement

Prove the design is ready to place, then qualify the placement it produces.

CHAPTER 06
Placement•Sanity and command sheets

Pre-placement readiness

Placement is the first stage that cannot be repaired by editing the floorplan alone, because it moves every cell that is not fixed. This chapter is the gate in front of it.

  • Fixed and preplaced baseline
  • dont_use and dont_touch
  • Placement blockages and padding
  • Tie-cell readiness
CHAPTER 07
Placement•Sanity and command sheets

Placement and post-placement qualification

Placement gives every cell a location, and every later stage inherits those locations.

  • Placement run and log
  • Placement legality
  • Fixed and dont_touch status preserved
  • Density and pin density
Clock tree

Clock tree synthesis

Qualify the clock tree setup, then the clock tree it builds and the timing that results.

CHAPTER 08
Clock tree•Sanity and command sheets

Clock tree synthesis readiness

Clock tree synthesis builds the clock network from what you tell it: which clocks exist, which pins are sinks, how the nets are routed, which cells may be used and what skew

  • Clock definitions and propagation state
  • Constants, clock sense and gating
  • Clock net routing rules
  • Clock cell lists
CHAPTER 09
Clock tree•Sanity and command sheets

CTS and post-CTS qualification

Clock tree synthesis replaces an ideal clock with a real network of buffers, wires and gates, and every later timing number depends on it.

  • CTS prerequisites and specification
  • CTS run and log
  • Clock tree report and clock DRVs
  • Skew groups and insertion delay
Routing

Routing and optimisation

Qualify global and early routing, detailed routing and post-route optimisation.

CHAPTER 10
Routing•Sanity and command sheets

Global and early routing qualification

Placement and clock tree synthesis decide where cells and clock wires go. Global routing asks the next question: is there room for every other wire?

  • Routing set-up record
  • Clock routing attributes
  • Route readiness and pin access
  • Early global route run and log
CHAPTER 12
Routing•Sanity and command sheets

Post-route optimisation qualification

After detailed routing the wires are real, so the delays are real too, and some of them are worse than the plan assumed.

  • Modes in force at entry
  • Analysis view coverage
  • Baseline timing with detailed extraction
  • Post-route optimisation run
Finish and handoff

Finishing, signoff and handoff

Qualify chip finishing, extraction and signoff correlation, ECO changes and the final handoff.

CHAPTER 13
Finish and handoff•Sanity and command sheets

Chip finishing and post-fill qualification

After routing and post-route optimisation, the design still has to be finished: filler, tap, end-cap and decap cells are added, and dummy metal is inserted to even out density.

  • Filler settings
  • Filler gaps
  • Tap, end-cap, decap
  • Placement with fill
CHAPTER 14
Finish and handoff•Sanity and command sheets

Extraction and signoff correlation

Every delay after routing rests on the resistance and capacitance that an extractor reads from the wires.

  • Mode and RC corner record
  • Extraction run and RCDB
  • Annotation coverage
  • SPEF out and in
CHAPTER 15
Finish and handoff•Sanity and command sheets

ECO and incremental requalification

A late change is the most likely thing to damage a design that was already qualified.

  • Baseline checkpoint and snapshots
  • ECO settings and interactive commands
  • Netlist-driven ECO and netlist comparison
  • Place and route the ECO cells
CHAPTER 16
Finish and handoff•Sanity and command sheets

Final implementation handoff

Handoff is the point where the implementation database stops being a working session and becomes a set of files that other teams and tools read.

  • Run identity and final summary
  • Physical closure on the frozen database
  • Timing on the frozen database
  • Save and restore proof
Second PDF

Cheat sheets book

The second PDF in your download. It comes with the handbook in the same payment and is not sold separately.

CHEAT SHEETS PDFIncluded, no extra payment
Companion to the handbook•83 pages

Cadence Innovus Qualification Cheat Sheets

Commands and what they produce, for all 16 qualification stages, each with a sanity check sheet and a command sheet. The commands are Legacy UI commands, as in the handbook.

  • Sanity check sheets: for each check, the command that answers it and what a healthy result, a result to review and a hard stop look like
  • Command sheets: each command grouped by task, with what it produces
  • The same sheets close every chapter online, so you can read them free. The PDF gathers them into one book to keep beside the tool

One payment of 199 rupees gives you both PDFs: the 290-page handbook and this 83-page cheat sheet book.

Before you start

How to use this handbook

What each chapter contains, and the matrix of stages, checks and reports.

BEFORE YOU START

How to use this handbook

Every chapter answers one question: how do we prove that this stage is configured correctly, healthy enough, and ready for the next stage? The answer is always evidence from a report, read against a project threshold, with a recorded decision.

0.1 Scope of this edition

This edition covers all sixteen chapters, from tool and session qualification to final handoff. Every chapter ends with two cheat sheets: a sanity check cheat sheet, which lists each check with what healthy, review and hard-stop results look like, and a command cheat sheet, which lists the chapter's commands and what each one produces. The Legacy UI and Common UI Tcl script packages follow in a later edition. Options and defaults can change between Innovus releases, so a script written from this book should be checked against the help of the release that will run it.

The handbook is written for engineers who already know what placement, clock tree synthesis and routing are. It does not teach the algorithms. It teaches how to decide whether the output of each step can be trusted.

0.2 Legacy UI and Common UI

Innovus has two command interfaces. The Legacy UI uses camelCase commands such as checkDesign and timeDesign. The Stylus Common UI, started with innovus -stylus, uses snake_case commands and a database attribute model built around set_db and get_db. It is tempting to translate one into the other by changing the case of the name. That does not work. Two commands with similar names can differ in default behaviour, object scope, the analysis context they use, and what they write.

The material provided for this edition documents the Legacy UI in full. For the Common UI, only the commands that appear in the Innovus+ Rapid Adoption Kit lab could be confirmed. Thus, every command card prints the Legacy syntax, and prints a Common UI form only when it was confirmed. Where it was not, the card says so, and the item stays open until it is confirmed against the Stylus Common UI Text Reference and Migration Guide.

0.3 Labels used in this book

LabelMeaning
Verified (Legacy reference)The command and every option shown exist in the Innovus Legacy text reference, and the combination is used the way the reference describes. Checked against documentation, not executed.
Verified (RAK)A Common UI form that appears in the Innovus+ Rapid Adoption Kit lab, which runs Innovus with -stylus.
Not yet verifiedNot confirmed in the provided material. Never printed as runnable code.
Environment-specificReal, but depends on the project: library pin names, file paths, methodology choices.
Illustrative valuesNumbers, names and counts made up for teaching. They are not thresholds.
Synthetic report, not tool outputA report excerpt written for teaching. The format is simplified and it did not come from a tool run.

Each command also carries its effect on the session, because qualification commands are supposed to observe the design, not change it. The effect is one or more of: reads or reports only, adds GUI violation markers, changes analysis configuration, updates the design database, writes files, or runs an expensive analysis. A script that is meant to check a stage should contain only the first three kinds unless a step deliberately prepares the next stage.

0.4 Stages and gates

The chapters follow the order of a typical block implementation, shown in Figure 1. The order is an organisation of the material, not a claim that every team runs the same sequence. Floorplan and power planning often iterate, pre-placement checks are sometimes merged into placement, and any ECO sends the flow back to the stage it disturbs. Each arrow carries a gate: the point where the evidence for the stage is reviewed and a decision is written down.

1 Sessionexit gate 12 Importexit gate 23 SDC / MMMCexit gate 34 Floorplanexit gate 45 Power planexit gate 56 Pre-placeexit gate 67 Placementexit gate 78 CTS readyexit gate 89 CTSexit gate 910 Global routeexit gate 1011 Detail routeexit gate 1112 Post-route optexit gate 1213 Finishingexit gate 1314 Extractionexit gate 1415 ECOexit gate 1516 Handoffexit gate 16ECO loop: rerun the gates that the change invalidates (Chapter 15)exit gate: evidence reviewed, decision recorded
Figure 1. The sixteen stage gates and the ECO loop
Read it. The small amber bars are exit gates. The dashed red line is the ECO loop: after a change, the flow returns to the earliest stage the change can disturb and reruns every gate from there.

0.5 The five qualification statuses

A check ends in exactly one of five statuses. The important part is the order in which we decide, shown in Figure 2. Before asking whether a result is good, we ask whether the check applies to this flow, and then whether it actually ran in the right context. A check that never ran cannot pass, and a report that does not say what it covered is not evidence of anything.

StatusUse it when
PASSThe check ran in the required context, the report shows its coverage, and every finding is within the project threshold.
WARN / REVIEWFindings exist that are normal at this stage, or need an explanation or an approved waiver before the gate closes.
HARD STOPA finding that makes later results meaningless. Fix it and rerun the gate before continuing.
NOT EVALUATEDThe check did not run, ran without the required view, data or licence, or produced output that does not show what it covered.
NOT APPLICABLEThe feature is not part of this flow, for example power-intent checks in a single-supply block. State the reason once.

Thresholds come from three places: the libraries (for example maximum transition and capacitance), the foundry (rules and decks), and the project methodology (utilisation targets, margins, waiver policy). This book does not invent universal numbers for any of them. Where a number appears in an example, it is marked illustrative.

Is the feature inthis flow?NOT APPLICABLEsay why, oncenoyesDid the check run onthe right view and data?NOT EVALUATEDmissing view, licence, inputnoyesDoes the report showwhat it covered?noNOT EVALUATEDempty is not cleanyesCompare against project thresholdsand approved waiversPASSwithin limitsWARN / REVIEWexplain or waiveHARD STOPfix, then rerun the gate
Figure 2. Deciding a qualification status
Read it. The three questions on the top row are about whether the evidence exists. Only the bottom row is about whether the design is good. An empty report lands in NOT EVALUATED, not PASS.

0.6 How a command card reads

Each check is written as a card with the same rows, so a reader can jump straight to the part they need. The first rows say what the check is for: the question it answers and the state the design must be in. The middle rows give the Legacy syntax, the Common UI status, the options and the effect on the session. The last rows tell the reader how to judge the result: the fields worth reading, what healthy, warning and hard-stop results look like, the usual misuse, the fix, and what to rerun after it. The verification row states what the syntax was checked against. After every chapter, a two-column cheat sheet lists the commands of that chapter and what each one produces.

OVERVIEW

Master stage, check and report matrix

The first table below maps report families to stages. A filled circle means the family is primary evidence at that stage, an open circle means it is supporting evidence, and a dash means it is not normally read at that stage. The columns follow the sixteen chapters, so you can see where a check moves to as the design matures.

Table 1. Report families by stage, stages 1 to 16.
Report family12345678910111213141516
Tool, release, UI, log and messages●●●●○○○○○○○○○○○●
Library, technology and database status○●○○--------○---
Design inventory and import warnings-●○-----------○●
Clocks, constraints, exceptions, unconstrained paths--●--○-●●--○--○●
MMMC configuration and active-view coverage--●--○-○○--○○●○●
Setup and hold timing by view and path group--○--○●○●-○●-●●●
Transition, capacitance and fanout limits--○--○●-●-○●-○●○
Placement legality, utilisation, density, congestion---○○○●--○---○○-
Macro and pin-access quality---●--○--○○○----
PG connectivity and power analysis-○--●----○○-●-○●
Clock-tree coverage, skew, latency, clock DRVs-------●●--○--○-
Routing completion, opens, shorts, geometry, antenna---○-----●●○●-●●
Counts, area, buffers, physical-only cells-●-○--○-○--○●-○●
Parasitic extraction and annotation coverage--○------○-○-●○●
Post-ECO deltas and cross-view regressions--------------●●
Final handoff completeness---------------●

Three rules apply to every cell of this table. First, record the context with the report: release, UI, checkpoint, stage and analysis view. A report without its context cannot be compared with the next run. Second, say whether the report is preliminary, implementation-level or signoff evidence. A congestion map before placement is preliminary, and treating it as proof of routability is a common mistake. Third, pair reports that can mislead on their own. Timing slack needs view coverage and unconstrained-path counts beside it, and a clean connectivity report needs the list of nets that were excluded from it.

Table 2. Evidence class by stage
StagePreliminary evidenceImplementation evidenceComplement needed to avoid a wrong conclusion
1 Session-version, UI, log, non-default modesmethodology baseline of required release and settings
2 Importgate count, areacheckDesign, check_design, checkNetlistsynthesis netlist counts for comparison
3 Constraintspre-place timing summaryview list, check_timing, coverageunconstrained and untested counts beside WNS
4 Floorplanearly congestioncheckFPlan, checkPlace, checkPinAssignmentproject utilisation and channel budgets
5 Power planearly rail estimatesPG connectivity, via and geometry checksthe power-intent and grid specification
6 Pre-placecongestion estimateblockage, tie, dont_use and settings checksthe ready-for-placement gate record
7 Placementestimated-wire timingcheckPlace, density, congestion, preCTS timingview coverage beside every slack figure
8 CTS ready-clock specification and clock-net checksthe intended clock plan to compare against
9 CTSideal-to-propagated changeclock-tree reports, skew, post-CTS timinghold and setup in every active view
10 Global routeoverflow estimatecongestion and overflow reportsa detailed-route result before routability is claimed
11 Detail route-verify_drc, verifyConnectivity, antennathe list of nets excluded from the checks
12 Post-route opt-postRoute timing and DRV, physical re-checksextraction mode and SI setting beside slack
13 Finishing-fill, well-tap, antenna and DRC after filltiming re-run after fill
14 Extraction-in-tool RC and annotation coveragesignoff-tool correlation
15 ECO-delta checks per changethe rerun matrix for that change type
16 Handoff-manifest, summary and read-back checksthe signoff-tool run, which this book does not replace