Floorplan, macro and pin qualification
4.1 Stage purpose
A floorplan defines the die and core boxes, the standard-cell rows, the macro locations and orientations with their halos, the placement and routing blockages, and the boundary pins. The vocabulary is shown in Figure 6. The die box (the design shape) is the outline of the block. The core box is the area inside it where rows exist and standard cells can be placed. A halo is a keep-out margin around a macro, and a channel is the space left between a macro, or its halo, and a neighbouring macro or the core edge.
Each of these objects can be legal and still be a problem. A channel can be legal and too narrow to route. A pin can be on a legal layer and on the wrong side of the block. Thus, this chapter uses two kinds of evidence: legality checks from the tool, and comparisons against the floorplan specification and project budgets.
4.2 Entry prerequisites
| Must already be true | Why |
|---|---|
| Chapters 1 to 3 passed | Floorplan decisions use the constraints, for example which pins are timing-critical. |
| A floorplan specification gives die size, core offsets, macro placement intent and the pin plan | The geometry checks compare against it. |
| Project budgets for utilisation, channel width and congestion exist | This book does not set those numbers. |
| Macro LEF abstracts include pins and blockages | Pin access and channel analysis depend on them. |
4.3 Relevant files and analysis context
The floorplan comes either from commands in the flow or from an imported floorplan file. Either way, what the checks see is the database in memory. The checks in this chapter are geometric and do not need a timing view, except where pin placement is judged against timing-critical ports.
The behaviour of checkFPlan depends on setFPlanMode -checkTypes: parameters set with setFPlanMode are used automatically whenever checkFPlan runs. The check types include basic, fence, macroPin, color, powerDomain, place, narrowChannel and others, with all selecting every type. The default is basic only. The blockOnly type bundles basic, oddEvenSiteRow, macroPin and color. The macroPin check works only when the block snap rule is LayerTrack, and narrowChannel needs a width threshold in microns. Thus, the setFPlanMode setting must be recorded with the report, because two runs of checkFPlan with different modes check different things, and a default run says nothing about macro pins or channels.
4.4 Checks and command cards
4.4.1 Pre-stage checks
Before the floorplan is built, the only checks are on the inputs: the floorplan specification is the released version, and every macro in the netlist appears in it. The second is easy to automate by comparing the macro list from the specification with the macro instances in your netlist report. The query that lists block instances depends on your database, so confirm attribute names with dbGet top.insts.? before scripting it.
4.4.2 Post-stage checks
| Question it answers | Are the die and core boxes the size and position the specification says? |
|---|---|
| Stage | After floorplan |
| Product | Innovus Implementation. The reference entry names no separate licence requirement for this command. |
| Required state | Floorplan created. |
| Legacy UI | dbGet top.fplan.boxes dbGet top.fplan.coreBox |
| Common UI | Not yet verified No Common UI form is printed. The provided files do not document one. |
|---|---|
| Mapping | Not established in the provided documentation |
| Options used | No options used. |
| Scope and view | Top cell. |
| Effect on session | reads or reports only |
| Output | Box coordinates as Tcl lists. |
| Fields that matter | Lower-left and upper-right coordinates of each rectangle of the design shape and of the core box. A non-rectangular design needs every rectangle, not the bounding box. |
| Healthy | Coordinates equal the specification. |
| Warning | A core offset that differs from the specification by a small amount; snapping is one possible cause, not verified. |
| Hard stop | Die size different from the specification, which changes everything downstream including the package or parent-level plan. |
| Common misuse | Comparing in the wrong units. Record the unit the values are reported in, and confirm it once against a known dimension such as the row height. |
| Root cause and fix | Correct the floorplan command or file. |
| Rerun after a fix | Rebuild the floorplan; rerun every card in this chapter. |
| Verification | Legacy syntax checked against the Innovus Legacy text reference. |
| Question it answers | Are rows, sites, grids, blocks and pins legal, and what is the target and effective utilisation? |
|---|---|
| Stage | After floorplan |
| Product | Innovus Implementation. The reference entry names no separate licence requirement for this command. |
| Required state | Floorplan created; setFPlanMode check types set and recorded. |
| Legacy UI | getFPlanMode -checkTypes
setFPlanMode -checkTypes {blockOnly narrowChannel} -narrowChannelThreshold <w>
checkFPlan -reportUtil -outFile <f> |
| Common UI | Not yet verified No Common UI form is printed. The provided files do not document one. |
|---|---|
| Mapping | Not established in the provided documentation |
| Options used | -checkTypes selects what checkFPlan checks. The default is basic. narrowChannel needs -narrowChannelThreshold, and macroPin needs the LayerTrack block snap rule.-reportUtil reports target utilisation (TU) and effective utilisation (EU) for the whole design, for fences, and for regions.-outFile writes the detailed results to a file. |
| Scope and view | Top cell, fences and regions. |
| What it checks | Among other things, alignment of die box, core box, rows, blocks, pads and cells to the FinFET grid when one is defined; row orientation against the site SYMMETRY; and pin snapping to tracks. A fence or region with EU at or above 100 percent is changed to a guide by placement. |
| Effect on session | adds GUI violation markers; changes analysis configuration; writes files. Some commands in this card only read or report. |
| Output | Violation markers in the design window and a detail file. |
| Fields that matter | Violations by type; TU and EU per design, fence and region. |
| Healthy | No violations for the recorded check types. TU and EU within the project budget. |
| Warning | EU noticeably higher than TU, which means blockages and other floorplan constraints remove more area than planned. |
| Hard stop | Off-grid blocks, illegal row orientation, EU at or above 100 percent in a fence or region, or EU above the project limit. |
| Common misuse | Running it with the default check types and reading it as proof for macro pins or channels, or comparing runs made with different setFPlanMode settings. Its utilisation also differs from the density printed by timeDesign, because checkPlace counts cell padding and timeDesign does not. |
| Root cause and fix | Snap blocks to the grid, correct row creation, or re-budget area. |
| Rerun after a fix | Rerun F-02 and F-03. |
| Verification | Legacy syntax checked against the Innovus Legacy text reference. |
| Question it answers | Is every macro placed, fixed, inside the core, on grid, with its halo, free of overlaps, and separated by wide enough channels? |
|---|---|
| Stage | After macro placement |
| Product | Innovus Implementation. The reference entry names no separate licence requirement for this command. |
| Required state | Macros placed. |
| Legacy UI | dbGet -e -p top.insts.pStatus fixed checkPlace <report_file> checkPlace -macroBlockage <report_file> dbGet top.insts.pHaloBox report_narrow_channel -width <w> |
| Common UI | Not yet verified No Common UI form is printed. The provided files do not document one. |
|---|---|
| Mapping | Not established in the provided documentation |
| Options used | -e -p returns pointers to instances whose placement status is fixed. -e prints an empty result instead of 0x0, so a count is not wrong by one.violationReportFileName names the violation report that checkPlace writes.-macroBlockage also checks overlap between hard macros and macro-only blockages, which are ignored by default.pHaloBox is a halo attribute of instances; compare it with the specified halo. The per-macro query was not run.-width is the channel width to judge against, from the project budget. |
| Scope and view | Whole design. checkPlace treats preplaced instances and macros as FIXED. Halos count in its overlap check. |
| Effect on session | adds GUI violation markers; writes files. Some commands in this card only read or report. |
| Output | A list of fixed instances; a checkPlace violation report and markers; narrow channel boxes. |
| Fields that matter | Number of fixed instances against the macro list; the number of unplaced macros that checkPlace prints; overlap, out-of-core, grid and orientation violations; region and fence violations; halo size; narrow channels. |
| Healthy | Fixed count equals the macro list; no checkPlace violations for macros; no channel below the budget width. |
| Warning | Fixed standard cells that the specification does not mention, such as preplaced tap or spare cells. |
| Hard stop | A macro left unplaced or not fixed, any macro overlap, out-of-core or off-grid violation, or a channel below the budget width. |
| Common misuse | Treating a clean checkPlace as the only proof. checkPlace treats macros as FIXED, yet its violation list says it does not check fixed macros for blockage violations. Confirm overlap detection once with a deliberately overlapped test macro. |
| Root cause and fix | Correct the macro location, halo or status in the floorplan. |
| Rerun after a fix | Rerun F-03, F-02 and F-05. |
| Verification | Legacy syntax checked against the Innovus Legacy text reference. |
| Question it answers | Are boundary pins on allowed layers, on track, correctly spaced and not overlapping? |
|---|---|
| Stage | After pin placement |
| Product | Innovus Implementation. The reference entry names no separate licence requirement for this command. |
| Required state | Pins placed. |
| Legacy UI | checkPinAssignment -outFile <f> |
| Common UI | Not yet verified No Common UI form is printed. The provided files do not document one. |
|---|---|
| Mapping | Not established in the provided documentation |
| Options used | -outFile writes the detailed results to a file. |
| Scope and view | Top cell, or a named partition in hierarchical flows. Where pins are assigned with early global route, run it after that step. |
| Effect on session | updates the design database; writes files |
| Output | A pin check report, also written to |
| Fields that matter | Unplaced pins; pins on the wrong layer for their side, outside the reserved layer range, on the same location as a pin of another net, off track, or violating spacing to blockages and power. |
| Healthy | No violations, and the pin order and side match the pin plan where the plan is entered as pin guides or groups. |
| Warning | Pins placed but not yet matched to the parent pin plan in a hierarchical flow. |
| Hard stop | Unplaced or overlapping pins, pins off track, or pins on a side that the pin plan does not allow. |
| Common misuse | Treating a clean legality report as proof the pin plan is right. Legality says nothing about whether the pin is on the side its timing path needs. Same-net pins at one location count as overlap only with -reportSameNetPinAsOverlap, and regular wires are not considered. |
| Root cause and fix | Replace the pins from the pin plan; fix the plan if the layer range is wrong. |
| Rerun after a fix | Rerun F-04 and F-05. |
| Verification | Legacy syntax checked against the Innovus Legacy text reference. |
| Question it answers | Does the floorplan leave enough routing resource, especially in macro channels? |
|---|---|
| Stage | After macro placement and an initial standard-cell placement |
| Product | Innovus Implementation. The reference entry names no separate licence requirement for this command. |
| Required state | Floorplan complete and standard cells placed. Without that placement the result shows macro and blockage effects only and is not a routability verdict. |
| Legacy UI | earlyGlobalRoute reportCongestion -hotSpot -overflow |
| Common UI | Not yet verified No Common UI form is printed. The provided files do not document one. |
|---|---|
| Mapping | Not established in the provided documentation |
| Options used | -hotSpot reports the local hotspot score: the largest and the total contiguous area of gcells with routing overflow.-overflow reports horizontal and vertical overflow. |
| Scope and view | Whole design. |
| Cost and side effect | earlyGlobalRoute writes estimated routes into the database and takes runtime. It honours setRouteMode settings, so record them. reportCongestion needs a route to exist, and leaves blockage area out of the hotspot report unless -includeBlockage is given. The hotspot score depends on gcell size and technology, so do not compare it across technologies. |
| Effect on session | updates the design database; runs an expensive analysis. Some commands in this card only read or report. |
| Output | Early routes in the database; a congestion summary on the console. |
| Fields that matter | Horizontal and vertical overflow; hotspot score and bounding box per hotspot; maximum and total hotspot. |
| Healthy | Hotspot score and overflow within the project budget. Tool guidance calls a maximum hotspot score below 100 typically routable; the budget is the gate. |
| Warning | Within budget, but hotspots concentrated in one macro channel. |
| Hard stop | Hotspot score or overflow above the project budget. |
| Common misuse | Treating early global route as a real route: it is not DRC clean and must not be used for signal integrity analysis. A pass before power planning also does not carry over, because stripes and rails use routing tracks. |
| Root cause and fix | Widen channels, move or reorient macros, or add routing blockage guidance. |
| Rerun after a fix | Rerun F-02, F-03 and F-05. |
| Verification | Legacy syntax checked against the Innovus Legacy text reference. |
| Question it answers | Are the placement prerequisites the tool knows about all met? |
|---|---|
| Stage | Before power planning (Chapter 5) and placement (Chapter 6) |
| Product | Innovus Implementation. The reference entry names no separate licence requirement for this command. |
| Required state | Floorplan complete. |
| Legacy UI | check_design -type place -out_file <f> |
| Common UI | Not yet verified No Common UI form is printed. The provided files do not document one. |
|---|---|
| Mapping | Not established in the provided documentation |
| Options used | -type place runs the placement prerequisite checks of check_design.-out_file writes the full list. |
| Scope and view | Whole design. |
| Flow behaviour | If check_design finds errors, the current script stops. The tool treats these findings as errors, so before the rails and cells exist the stop is expected. |
| Effect on session | writes files |
| Output | A violation table; the out file holds the full list as a Tcl dictionary. |
| Fields that matter | PG rail alignment, pin access issues, missing followpins on standard-cell rails, misaligned well-tap cells and missing termination cells. |
| Healthy | No errors. |
| Warning | Followpin, well-tap or termination-cell findings before those rails and cells exist; record them and recheck after power planning. |
| Hard stop | Pin access issues or PG rail misalignment on rows where standard cells will be placed. |
| Common misuse | Running it once at the end of the floorplan and not again after power planning, which adds the rails this check reads. |
| Root cause and fix | Fix the floorplan, rail or physical-cell setup that the finding names. |
| Rerun after a fix | Rerun after power planning, as the gate before placement in Chapter 6. |
| Verification | Legacy syntax checked against the Innovus Legacy text reference. |
| Question it answers | What does the PG connectivity look like before any rings or stripes exist? |
|---|---|
| Stage | After floorplan, before power planning |
| Product | Innovus Implementation. The reference entry names no separate licence requirement for this command. |
| Required state | Floorplan complete; logical PG connections made with globalNetConnect (Chapter 2), otherwise every PG pin is open for a logical reason. |
| Legacy UI | verifyConnectivity -net {VDD VSS} -type special -noAntenna -report <f> |
| Common UI | Not yet verified No Common UI form is printed. The provided files do not document one. |
|---|---|
| Mapping | Not established in the provided documentation |
| Options used | -net {VDD VSS} limits the check to the named nets; use the PG net names of your design.-type special checks special wires and vias only. Unconnected terminals of both kinds are still reported unless -noUnConnPin is given, which is why -net is needed to keep this a PG snapshot.-noAntenna skips the geometric antenna part of the check.-report writes the report file. |
| Scope and view | The named PG nets. |
| Side effect | The command does not change the database unless the design is saved, in which case the markers are saved too. |
| Effect on session | adds GUI violation markers; writes files |
| Output | Markers and a report. |
| Fields that matter | Opens and unconnected PG pins per net. |
| Healthy | Recorded as a baseline; opens are expected until power planning. |
| Warning | Some macro PG pins already show as connected because floorplan preroutes exist; record which. |
| Hard stop | None at this stage; this snapshot is a baseline for Chapter 5. |
| Common misuse | Reading the expected opens as a failure, or reading this snapshot as power-plan evidence. |
| Root cause and fix | Nothing to fix yet. |
| Rerun after a fix | Repeated as a real check in Chapter 5. |
| Verification | Legacy syntax checked against the Innovus Legacy text reference. |
4.5 Required reports, artefacts and how to read them
| Report | Fields that support qualification | Evidence class |
|---|---|---|
| Geometry snapshot (F-01) | die and core coordinates with units | implementation |
| checkFPlan detail file and TU/EU (F-02) | violation types; utilisation by design, fence and region; the setFPlanMode check types | implementation |
| checkPlace report (F-03) | macro violations | implementation |
| checkPinAssignment report (F-04) | pin violations | implementation |
| Congestion summary (F-05) | overflow percentages, hotspot scores and bounding boxes | preliminary |
| check_design place out file (F-06) | placement prerequisites | implementation |
reportCongestion -hotSpot -overflow ## illustrative excerpt Overflow: 210 = 7 (0.01% H) + 202 (0.33% V) [hotspot] Top hotspot bbox hotspot score [hotspot] 1 310.2 120.5 402.8 260.0 142.00 [hotspot] 2 32.2 262.6 126.5 300.8 31.40
Let us read it against Figure 6. Overflow is small over the whole block, which is why it is the least useful number here. The top hotspot score of 142 is above the tool guidance of 100, and its bounding box, compared with the macro location, falls in the narrow channel to the right of RAM0. A small overall overflow hides a single blocked channel. Thus, the decision follows the hotspot and its location, not the overall figure.
4.6 Healthy, suspicious and hard-stop examples
| Finding | Status | Why |
|---|---|---|
| Die and core match the specification | PASS | The space is what everyone planned for. |
| EU well above TU | WARN / REVIEW | Blockages and other constraints cost more area than planned. |
| Macro channel below the budget width | HARD STOP | The channel is legal but too narrow to route. |
| Macro not fixed | HARD STOP | Placement can move it and invalidate the plan. |
| Overlapping or off-track pins | HARD STOP | Routing cannot connect them legally. |
| Legal floorplan, hotspot score or overflow above budget | HARD STOP | Legal is not routable; fix before placement. |
| PG opens before power planning | WARN / REVIEW | Expected; baseline for Chapter 5. |
| Power-domain checks in a single-supply block | NOT APPLICABLE | No power domains exist. |
4.7 Debugging, corrective action and reruns
Floorplan fixes have a wide blast radius. Moving one macro changes channels, congestion, pin access and, later, the power grid. It is prudent to rerun the full chapter after any macro move, rather than only the card that found the problem, because the next problem is usually in the neighbouring channel.
4.7.1 Worked example: a legal floorplan that will not route
Suppose F-02 and F-03 are clean: no violations, utilisation within budget, every macro fixed. The congestion summary above, however, shows the worst hotspot in the channel between RAM0 and the core edge. The halo leaves about a dozen tracks on the routing layers of that channel, while the macro has a row of pins facing it. Every check that tests legality passes, because a narrow channel is legal, while report_narrow_channel with the budget width lists the same channel. With an illustrative budget of 100, the score of 142 exceeds it, so the decision for F-05 is HARD STOP: move the macro to widen the channel or turn it so its pins face open area, then rerun F-02 to F-05. Note that the dozen tracks in this example is illustrative. The real count comes from the routing layer pitch and the channel width of your design.
4.8 Exit criteria and stage checklist
- Geometry. Die and core boxes equal the specification, with units recorded.
- Legality. checkFPlan clean with the recorded setFPlanMode check types, which are more than the default basic.
- Utilisation. TU and EU within the project budget.
- Macros. Every macro placed, fixed, with its halo, free of checkPlace violations, and no channel below the budget width.
- Pins. checkPinAssignment clean with no unplaced pins, and pin sides match the pin plan.
- Routability. Hotspot score and overflow within budget, repeated after power planning and placement.
- Prerequisites. check_design -type place has no errors.
- Baseline. Special-net connectivity snapshot stored for Chapter 5.
Thus, a floorplan is qualified when it is legal, matches its specification, and leaves the routing resource the design needs. A floorplan that is only legal tends to pass every check until detailed routing, and then fails in the most expensive place to fix it. In the next chapter, Chapter 5 builds the power grid on this floorplan and checks its connectivity.
4.9 Sanity check cheat sheet: Floorplan, macro and pins
One row per command card. Read left to right: the check, the command that answers it, then what a healthy result, a result to review and a hard stop look like. Judge every row against your project budgets, because this book sets no universal limits.
| Card | Check and when | Command | Healthy | Review | Hard stop |
|---|---|---|---|---|---|
| F-01 | Die and core geometry After floorplan | dbGet top.fplan.boxesdbGet top.fplan.coreBox | Coordinates equal the specification. | A core offset that differs from the specification by a small amount; snapping is one possible cause, not verified. | Die size different from the specification, which changes everything downstream including the package or parent-level plan. |
| F-02 | Floorplan legality and utilisation After floorplan | getFPlanMode -checkTypessetFPlanMode -checkTypes {blockOnly narrowChannel} -narrowChannelThreshold <w>checkFPlan -reportUtil -outFile <f> | No violations for the recorded check types. TU and EU within the project budget. | EU noticeably higher than TU, which means blockages and other floorplan constraints remove more area than planned. | Off-grid blocks, illegal row orientation, EU at or above 100 percent in a fence or region, or EU above the project limit. |
| F-03 | Macro placement and overlap After macro placement | dbGet -e -p top.insts.pStatus fixedcheckPlace <report_file>checkPlace -macroBlockage <report_file> | Fixed count equals the macro list; no checkPlace violations for macros; no channel below the budget width. | Fixed standard cells that the specification does not mention, such as preplaced tap or spare cells. | A macro left unplaced or not fixed, any macro overlap, out-of-core or off-grid violation, or a channel below the budget width. |
| F-04 | Pin assignment After pin placement | checkPinAssignment -outFile <f> | No violations, and the pin order and side match the pin plan where the plan is entered as pin guides or groups. | Pins placed but not yet matched to the parent pin plan in a hierarchical flow. | Unplaced or overlapping pins, pins off track, or pins on a side that the pin plan does not allow. |
| F-05 | Early routability After macro placement and an initial standard-cell placement | earlyGlobalRoutereportCongestion -hotSpot -overflow | Hotspot score and overflow within the project budget. Tool guidance calls a maximum hotspot score below 100 typically routable; the budget is the gate. | Within budget, but hotspots concentrated in one macro channel. | Hotspot score or overflow above the project budget. |
| F-06 | Ready for placement Before power planning (Chapter 5) and placement (Chapter 6) | check_design -type place -out_file <f> | No errors. | Followpin, well-tap or termination-cell findings before those rails and cells exist; record them and recheck after power planning. | Pin access issues or PG rail misalignment on rows where standard cells will be placed. |
| F-07 | Special-net connectivity snapshot After floorplan, before power planning | verifyConnectivity -net {VDD VSS} -type special -noAntenna -report <f> | Recorded as a baseline; opens are expected until power planning. | Some macro PG pins already show as connected because floorplan preroutes exist; record which. | None at this stage; this snapshot is a baseline for Chapter 5. |
4.10 Command cheat sheet: Floorplan, macro and pins
Legacy UI commands. Angle brackets are placeholders, and values shown are examples, not project limits.
| Command | What it produces |
|---|
| Geometry and grids | |
|---|---|
dbGet top.fplan.boxes | The design shape coordinates. |
dbGet top.fplan.coreBox | The core box coordinates. |
get_snap_grid_info -type placement | The current placement snap grid settings. |
get_snap_grid_info -type manufacturing | The current manufacturing grid settings. |
getAllLayers metal | The list of metal layers, to confirm the routing stack the floorplan uses. |
| Floorplan legality and utilisation | |
|---|---|
getFPlanMode -checkTypes | The check types checkFPlan will run. Record it with every checkFPlan report. |
setFPlanMode -checkTypes {blockOnly narrowChannel} -narrowChannelThreshold <w> | Selects the block-level types (basic, oddEvenSiteRow, macroPin, color) and the narrow-channel check. The threshold is in microns and is required for narrowChannel. macroPin is checked only with setFPlanMode -snapBlockGrid LayerTrack. Changes the session. |
setFPlanMode -checkTypes all | Selects every checkFPlan check type, including power domain, partition and fence types that add noise in a flat block. Changes the session. The default is basic. |
checkFPlan | Floorplan violation markers for the selected check types. |
checkFPlan -outFile <f> | The same with the detail written to a file. |
checkFPlan -reportUtil -outFile <f> | Adds target (TU) and effective (EU) utilisation for the design, fences and regions. |
checkFPlanSpace -outfile <f> | Floorplan spacing rule violations, with markers. |
reportUnsnapBlocks | Blocks that are not snapped according to the floorplan snap preferences. |
checkDesign -floorplan -noHtml -outfile <f> | Off-grid tracks, instances not snapped to row sites, unplaced I/O pins, off-grid PG preroutes. |
check_design -type place -out_file <f> | PG rail alignment, pin access issues, missing followpins, misaligned well-tap cells and missing termination cells. Stops the script on errors. |
check_library -place -all_lib_cell -file <f> | Library cells that cause problems against the existing preroutes, such as bad DRC geometry or bad pin access. Meaningful once preroutes exist. |
violationBrowserReport -all -report <f> | Every violation flagged so far by the verification commands, written to one file. |
| Macros and channels | |
|---|---|
dbGet top.insts.pHaloBox | The halo box attribute of instances, to compare macro halos with the specification. The attribute name is listed by dbGet top.insts.? and the per-macro query was not run. |
dbGet -p top.insts.pStatus fixed | Pointers to every fixed instance; compare the count with the macro list. With no match it prints 0x0, so use -e when counting. |
checkPlace <report_file> | Overlap, out-of-core, off-grid, orientation, region and fence violations, with markers, and the number of unplaced macros. Treats macros as fixed. Halos count in the overlap check. |
checkPlace -macroBlockage <report_file> | Adds overlap checks between hard macros and macro-only blockages, which are ignored by default. |
checkPlace -noHalo <report_file> | The overlap check without block halos, using the place-and-route boundary instead. |
checkMacroLLOnTrack | Hard macros whose lower-left corner is not on a Metal1/Metal2 track intersection. The default assumes those layers run in opposite directions, so confirm the layer directions in your technology. Option usage not verified. |
check_macro_place_constraint | A check of the macro constraints that the macro placer will honour. |
report_narrow_channel -width <w> | A list of narrow channels between core, macros, halos and hard blockages (the default objects), judged against the given width. Returns the channel boxes. |
report_narrow_channel -width <w> -direction x | The same check in the x direction only. The default checks both directions. |
reportCellPad -file <f> | The cells with user padding and their padding. Padding counts in checkPlace utilisation. |
reportInstPad -all | The padding of every padded instance. |
| Pins | |
|---|---|
checkPinAssignment -outFile <f> | Pins on wrong layers, off track, overlapping, unplaced, or too close to blockages and power. Writes <design>.checkPin.rpt when no file is named. |
checkPinAssignment -report_violating_pin -outFile <f> | The same report listing every violating pin. |
checkPinAssignment -preCheck | A feasibility check that finds why pins stay unplaced in a fully abutted design. No other option can be combined with it. |
checkDesign -io -noHtml -outfile <f> | Unplaced I/O cells and pins, floating I/O pad pins, I/O pins tied to core cells. |
getPinAssignMode | The current pin assignment settings, such as the allowed layer range. |
reportPinAssignStatistics -outFile <f> | Pin QoR data per partition. For hierarchical flows. |
| Routability | |
|---|---|
earlyGlobalRoute | Estimated routes in the database for congestion and parasitic estimates. Use after placement. Not DRC clean; not for SI. |
reportCongestion | Average congestion and the local hotspot score. Needs a route to exist. Blockage area is left out of the hotspot report unless -includeBlockage is given. |
reportCongestion -hotSpot | The maximum and total hotspot area, the contiguous gcells with overflow. |
reportCongestion -hotSpot -num_hotspot 10 | The same, listing the given number of hotspots. |
reportCongestion -overflow | Horizontal and vertical overflow. |
reportCongestion -3d -overflow | Layer-based overflow from the 3D congestion map. |
reportDensityMap | A placement density map and report, threshold 0.75 by default. Use after placement. |
reportDensityMap -threshold 0.85 | The same, reporting only grids above 0.85. |
reportPinDensityMap | A pin density map and report. Use after placement. |
getDensityMapMode | The current density map settings, such as the threshold and grid. |
| Physical cells and power structure | |
|---|---|
verifyEndCap -report <f> | Markers for missing end-cap cells and end caps of the wrong type. Run after addEndCap. |
verifyEndCap -wrongLocation -report <f> | Adds a check that end caps sit in the right location. |
verifyWellTap -report <f> | Markers for missing well-tap cells and taps that break the distance rule, with the actual and rule distance. Run after addWellTap. |
report_pg_keepout | Every PG keepout box in the design. Option form not verified. |
reportPowerDomain -file <f> | Power-domain information. For multi-supply designs; not applicable to a single-supply block. |
| PG snapshot | |
|---|---|
verifyConnectivity -net {VDD VSS} -type special -noAntenna -report <f> | Opens and unconnected PG pins on the named PG nets, with markers. |
verifyConnectivity -type special -noUnConnPin -report <f> | Special-wire checks that ignore pins not connected to any other object. |
verifyPowerVia -net {VDD VSS} -report <f> | Missing power-grid vias where rails and stripes overlap. Meaningful once the grid exists. |
checkDesign -powerGround -noHtml -outfile <f> | Unconnected or wrongly tied PG pins. |