Placement and post-placement qualification

7.1 Stage purpose

Placement gives each movable standard cell a location. Global placement spreads the cells to shorten wires and, when timing constraints are loaded, to help timing and relieve congestion. Legalisation then moves every cell onto a row and onto the site grid, in a legal orientation and clear of its neighbours. The distance a cell moves in that step is its displacement. A site is the smallest unit of a row, and a row is a strip of sites with one cell height. Figure 10 shows both steps on a small window.

Placement density is the share of available sites that cells occupy, measured in a bin, which is a rectangular window of the core. A nearly full bin leaves little room for the buffers and resized gates that optimisation adds later.

Legal and healthy are different things. The right panel of Figure 10 passes every legality check and still has a dense bin. The 0.75 in the ledger is the default display threshold of the density report, not a limit. Your project budget sets the limit.

This chapter keeps four ideas apart. Tool completion means a command ended. Analysis coverage means a report examined what you needed it to examine, and an empty report is not a pass. Stage qualification means the evidence meets your project budgets. Signoff is a later stage and is not claimed here. Legality checks give implementation evidence. Congestion and timing numbers come from estimated routes and ideal clocks, so they are preliminary evidence.

7.2 Entry prerequisites

7.3 Relevant files and analysis context

The checks read the database in memory, so the settings that were active when placement ran matter. The reference lists setOptMode and setRouteMode as fully honoured by place_design, and setPlaceMode, setAnalysisMode and setExtractRCMode as honoured with exceptions. For example, hold analysis is not honoured, and clocks are treated as ideal even if setAnalysisMode asks for sdcControl. Record the non-default settings with report_command_mode -non_default and the placement settings with getPlaceMode before the run, and store them next to the reports.

Reports from timeDesign and optDesign go to the timingReports directory unless -outDir names another. Their file names carry the top cell name and the stage. Use one directory per run, so that the reports of two runs are never mixed in one comparison.

Two defaults change what you should expect. Pre-placement optimisation removes buffer trees unless -noPrePlaceOpt is given, so the instance count after placement is not expected to equal the count before it. Cell padding set with specifyCellPad reserves space around cells during placement, and checkPlace counts it in utilisation. Instance padding is a hard rule only when setPlaceMode -place_detail_honor_inst_pad is true. Record whether either kind of padding is in use.

Many flows run place_opt_design instead of place_design followed by optDesign -preCTS. The tool documentation says it can replace that pair, so there is then no point between placement and optimisation, and the L-07 baseline cannot be taken. In the place_opt_design V2 flow, the later clock_opt_design legalises first to remove overlaps left by optimisation, so an overlap found by L-02 at that point is expected. With setDesignMode -earlyClockFlow true, CCOpt builds a clock tree inside place_opt_design, so the CTS configuration of Chapter 8 is set before placement. Each card says which command wrote the report it reads.

Hold is not a qualification item at this stage. place_design does not honour hold analysis, and optDesign -preCTS cannot be combined with -hold. Ideal-clock numbers contain only the skew and uncertainty that the constraints state, so record those values with the run.

7.4 Checks and command cards

7.4.1 Pre-stage checks

Placement is the first stage that moves cells, so repeat three checks from earlier chapters before you run it. Record the FIXED instance count with dbGet -p top.insts.pStatus fixed and keep it as the baseline for card L-03. Confirm that the constraints are loaded, because without them place_design assumes non-timing-driven placement. If the block has scan chains, confirm that the scan information is loaded. The reference describes check_design -type place as the check to run before placement.

7.4.2 Post-stage checks

place_design
report_scan_chain -out_file <f>
scanTrace -verbose

checkPlace <report_file>

dbGet -p top.insts.pStatus fixed
dbGet top.insts.isDontTouch 1 -p
report_preserves -dont_touch

reportDensityMap -gridInRow <n> -threshold <d>
reportPinDensityMap

earlyGlobalRoute
reportCongestion -hotSpot -overflow

verifyEndCap -report <f>
verifyWellTap -report <f>
checkDesign -tieHiLo -noHtml -outfile <f>

timeDesign -preCTS -outDir <dir>

report_analysis_coverage -verbose {violated untested}

timeDesign -preCTS -drvReports -outDir <dir>
reportFanoutViolation -outfile <f>
report_constraint -drv_violation_type {max_transition max_capacitance max_fanout} -all_violators

check_timing -type loops
setOptMode -opt_fix_fanout_load true
optDesign -preCTS

7.5 Required reports, artefacts and how to read them

checkPlace placement.rpt                              ## illustrative excerpt
Begin checking placement ...
Pre-route DRC Violation:              0
Pin Access Violation:                 3
*info: Placed = 41820           (Fixed = 214)
*info: Unplaced = 0
Placement Density:58.20%(23120/39724)
Placement Density (including fixed std cells):59.10%(23480/39724)

reportDensityMap -gridInRow 10 -threshold 0.75
powerDomain TOP: bins with density > 0.75 = 0.617 % ( 6 / 972 )
bin size: 59 sites by 10 row(s). total 972 bins ( 36 by 27 )
density range #bins %
0.75 - 0.8 4 0.4115
0.8 - 0.85 2 0.2058
total 6 0.617

Suppose the recorded baseline is 214 FIXED instances. The synthetic report shows Fixed = 214 and Unplaced = 0, which is consistent with no object losing its status, because equal counts do not prove it: compare the instance lists of L-03. The three pin access violations are not a stop by themselves, but each needs a location and an owner. The numbers in this excerpt are illustrative.

The density report counts six of 972 bins above 0.75, and none above 0.85. The excerpt gives counts, not locations, so open the density map to see where the six bins are. Then compare their location with the congestion hotspots from L-05. Six bins in a macro channel is a different finding from six bins spread across the core.

timeDesign -preCTS -outDir run1_reports               ## illustrative excerpt
timeDesign Summary
Setup views included:
 setup_func_max
+--------------------+---------+---------+---------+---------+
| Setup mode         |   all   | reg2reg |reg2cgate| default |
| WNS (ns):          |  -0.142 |  -0.142 |   0.031 |   0.208 |
| TNS (ns):          |   -21.4 |   -21.4 |   0.000 |   0.000 |
| Violating Paths:   |     212 |     212 |       0 |       0 |
| All Paths:         |   20050 |   17980 |     440 |    1630 |
+--------------------+---------+---------+---------+---------+
| DRVs      | Nr nets(terms) | Worst Vio |
| max_cap   | 0 (0)          | 0.000     |
| max_tran  | 3 (3)          | 0.084     |
| max_fanout| 5 (5)          | 12        |
Density: 59.100%
Routing Overflow: 0.21% H and 0.14% V

Setup is negative only in the reg2reg group, at -0.142 ns, and the clock-gating and default groups are positive. The 212 violating paths are endpoint counts, as the reference explains, so the group figures are read separately. Because the clocks are ideal, this is preliminary evidence and says nothing about skew.

Two DRV lines need a decision. Optimisation is expected to repair the three transition violations, so you recheck them after L-10. The five fanout violations stay unless setOptMode -opt_fix_fanout_load is set before the run, which is why L-09 flags them as a warning. The summary also lists one setup view. If the plan needs two, this card is NOT EVALUATED for the other.

7.6 Healthy, suspicious and hard-stop examples

7.7 Debugging, corrective action and reruns

Repair in a fixed order: legality first (L-02), then routing resource (L-04 and L-05), then timing (L-07 to L-10). Optimisation on an illegal or congested placement is wasted work, because the next placement moves the cells again. Any change that moves cells makes every earlier result stale, so rerun the whole chapter and not only the card that found the problem.

7.7.1 Worked example: a legal placement with a dense channel

Suppose L-02 is clean, with Unplaced at zero. L-04 reports six bins above the project density limit in the channel beside macro RAM0, and L-05 shows a maximum hotspot score above the project budget in the same box. Legality passes, so the finding is about resource. Figure 10 shows the same mechanism in miniature. Bin A uses 33 of 36 sites against a display threshold of 27, so it is over by six sites, while bin B uses nine.

The decision for L-05 is HARD STOP. The reference offers two placement settings for this case. One raises the congestion effort. The other adds soft blockages in narrow channels between macros, which the placer honours and optimisation does not.

setPlaceMode -place_global_cong_effort high           ## illustrative sequence
setPlaceMode -place_global_auto_blockage_in_channel soft
place_design

After the new run, repeat the chapter from L-01. Expect the channel density to fall. Also check displacement and WNS, because spreading cells can lengthen some nets. Your project budgets, not the example numbers, decide when the channel is acceptable.