A data converter is the point where a continuous voltage becomes a number, or a number becomes a voltage. An analog-to-digital converter (ADC) samples and quantizes an input; a digital-to-analog converter (DAC) does the reverse. Every sensor interface, radio receiver, audio path and many on-chip monitors depend on one.
This lesson describes the two operations every ADC performs – sampling in time and quantizing in amplitude – and the figures of merit used to judge them. It then introduces the main ADC architectures and the basic DAC at concept level. The circuit blocks inside them are the ones from lessons 4 to 6: references, comparators, amplifiers and matched capacitors.
Reading time: about 9 minutes.
7.1 Sampling and the Nyquist criterion
An ADC takes a sample of its input at regular intervals set by the sampling frequency fs. The Nyquist criterion states that a band-limited signal can be reconstructed exactly from its samples only if fs is greater than twice the highest frequency in the signal. Half the sampling rate, fs/2, is called the Nyquist frequency.
When the input contains energy above fs/2, it does not disappear; it folds back into the band from 0 to fs/2 and becomes indistinguishable from a real low-frequency signal. This is aliasing. Let us consider fs = 100 MHz and an input tone at 70 MHz. The samples are identical to those of a 30 MHz tone (100 − 70), and nothing after the ADC can tell them apart. Thus, an analog anti-aliasing filter in front of the ADC is required to remove out-of-band energy before sampling.
The sample itself is taken by a switch and a capacitor – the sample-and-hold. As lesson 6 showed, the capacitor carries a kT/C noise of its own, and that sets a minimum capacitor size for a given resolution.
7.2 Quantization
An N-bit ADC maps its full-scale input range VFS onto 2ᴺ output codes. The width of one code is the least significant bit:
LSB = VFS / 2^N (7.1)For a 10-bit ADC with VFS = 1 V, one LSB is about 0.98 mV. Every input within one LSB maps to the same code, so the output differs from the input by a quantization error between −½ LSB and +½ LSB. Figure 7.1 shows the staircase transfer function of an ideal 3-bit ADC and the sawtooth error it leaves.
For an input that moves through many codes, the error is nearly uniformly distributed between −½ and +½ LSB, so it can be treated as noise with an rms value of LSB/√12. That is the quantization noise of an ideal converter.
7.3 SNR of an ideal converter
Let us consider a full-scale sine wave. Its amplitude is VFS/2, so its rms value is VFS/(2√2). The quantization noise from (7.1) is VFS/(2ᴺ·√12). The ratio gives
SNR = 20·log10( [VFS/(2·√2)] / [VFS/(2^N·√12)] )
= 20·log10(2^N) + 20·log10(√1.5)
= 6.02·N + 1.76 dB (7.2)Each extra bit adds about 6 dB. A 10-bit converter has an ideal SNR of about 62.0 dB, and a 12-bit converter about 74.0 dB. Equation (7.2) assumes the noise is spread over the full Nyquist band from 0 to fs/2. If the signal occupies a narrower band and the rest is filtered digitally, the in-band noise falls. Without any other technique, each doubling of the oversampling ratio improves SNR by about 3 dB, or half a bit. Section 7.6 shows how sigma-delta converters exploit this much more strongly.
7.4 Static errors: DNL and INL
A real ADC does not have perfectly equal code widths, mainly because of the mismatch described in lesson 6. Two static measures capture this:
- DNL (differential non-linearity) – the difference between the actual width of each code and the ideal 1 LSB, expressed in LSB. A code that is 1.3 LSB wide has a DNL of +0.3 LSB. A DNL of −1 LSB means the code never appears, a missing code.
- INL (integral non-linearity) – the deviation of each actual code transition from the ideal straight line, in LSB. It can be thought of as the accumulated DNL. The reference line is either the line through the end points or a best-fit line, and the datasheet or specification should say which.
The same definitions apply to a DAC, where the "width" is the size of each output step. A DAC whose DNL is greater than −1 LSB at every code is guaranteed to be monotonic – its output never falls when the code rises – which matters greatly when the DAC sits inside a control loop.
7.5 Dynamic performance and ENOB
A real converter also adds thermal noise, jitter of the sampling clock (lesson 8), and harmonic distortion. These are measured together by applying a pure sine wave and computing SINAD (signal-to-noise-and-distortion ratio) from the output spectrum. Rearranging (7.2) turns SINAD into an equivalent resolution:
ENOB = (SINAD − 1.76) / 6.02 (7.3)A 12-bit ADC is measured with a near-full-scale input and shows a SINAD of 65 dB.
ENOB = (65 − 1.76) / 6.02 ≈ 10.5 bits.
Its ideal SNR would be 74.0 dB, so about 9 dB – a factor of almost three in rms noise voltage – is lost to thermal noise, distortion and clock jitter. If the system needs 11 effective bits, this converter does not meet the requirement even though it outputs 12-bit codes.
Thus, the number of bits on the output bus says little on its own. ENOB, together with the sampling rate and the power, is what the system designer compares.
7.6 ADC architectures
Different architectures trade speed, resolution, power and area. Table 7.1 lists the four the reader will meet most often. The ranges are typical and move with each process generation.
| Architecture | Principle | Typical resolution | Typical use |
|---|---|---|---|
| Flash | 2ᴺ − 1 comparators compare the input with every threshold at once | 4 to 8 bits | Very high speed, often as a sub-block of other ADCs |
| SAR | Binary search, one bit per comparison, using a DAC | 8 to 16 bits | General purpose, sensors, low power |
| Pipeline | Cascade of stages, each resolving a few bits and amplifying the residue | 10 to 16 bits | High speed with moderate resolution |
| Sigma-delta | Oversampling with noise shaping, followed by a digital decimation filter | 16 to 24 bits | Audio, precision measurement |
7.6.1 Flash
A flash ADC is a resistor ladder that generates all 2ᴺ − 1 thresholds, a comparator at each tap, and an encoder that turns the resulting thermometer code into binary. It converts in a single comparison time, but the comparator count doubles with every bit, so area, power and input capacitance grow quickly.
7.6.2 SAR
The successive-approximation register (SAR) ADC in Figure 7.2 performs a binary search. After sampling, the logic sets the most significant bit, the DAC produces the corresponding voltage, and the comparator decides whether the input is above or below it. The bit is kept or cleared, and the process repeats for the next bit. An N-bit conversion takes N comparator decisions.
In many SAR designs the DAC is an array of binary-weighted capacitors that also performs the sampling, so it costs no extra circuit. SAR converters scale well with process, because most of their circuitry is digital logic and switches, and they are a common choice for on-chip general-purpose ADCs.
7.6.3 Pipeline
A pipeline ADC splits the conversion across several stages. Each stage resolves a few bits with a small flash ADC, subtracts the corresponding DAC value from its input, amplifies the remainder (the residue), and passes it on. All stages work at once on different samples, so the throughput is one sample per clock, at the cost of a latency of several clocks. The residue amplifiers are op-amps of the kind described in lesson 5, and they usually dominate power.
7.6.4 Sigma-delta
A sigma-delta (ΣΔ) modulator samples much faster than the Nyquist rate, uses a coarse quantizer – often a single bit – inside a feedback loop with an integrator, and thereby pushes quantization noise to high frequencies, away from the signal band. This is noise shaping. A digital decimation filter then removes the out-of-band noise and reduces the rate. A first-order loop improves SNR by about 9 dB per doubling of oversampling ratio, compared with 3 dB for oversampling alone. The approach trades speed for resolution and moves much of the work into digital logic.
7.7 DAC basics
A DAC generates an output proportional to its input code. The main families are:
- Resistor string – 2ᴺ equal resistors with a switch at each tap. Inherently monotonic, but large for high resolution.
- Binary-weighted – resistors, currents or capacitors weighted 1, 2, 4, 8 and so on. Compact, but the large most-significant element must match the sum of all others, so mismatch at the major code transitions can cause large DNL errors.
- Current-steering – arrays of matched current sources switched to the output, used for high-speed DACs. The mirrors of lesson 4 are its core.
- Segmented – a thermometer-coded array of equal units for the upper bits and a binary array for the lower bits, combining good DNL with reasonable size.
Beyond static accuracy, a high-speed DAC must limit glitches – short spikes when many bits switch at once at a major code transition – and its output settling time.
7.8 Interview questions
What is the Nyquist criterion and what happens if it is violated? The sampling rate must exceed twice the highest signal frequency. Otherwise, components above fs/2 alias into the band of interest and cannot be removed afterwards.
Derive the SNR of an ideal N-bit ADC. A full-scale sine has rms VFS/(2√2), quantization noise is LSB/√12 with LSB = VFS/2ᴺ, and the ratio gives 6.02N + 1.76 dB.
What do DNL and INL measure? DNL is the deviation of each code width from 1 LSB; INL is the deviation of the transfer curve from a straight line. DNL of −1 LSB means a missing code.
What is ENOB? The effective number of bits, (SINAD − 1.76)/6.02, which includes all real noise and distortion.
Compare SAR and sigma-delta ADCs. SAR uses a binary search at the Nyquist rate and suits medium resolution at low power; sigma-delta oversamples and noise-shapes to reach high resolution at lower bandwidth.
Key takeaways
- Sampling must satisfy Nyquist; an anti-aliasing filter removes energy above fs/2 before the ADC.
- Quantization error is uniform within ±½ LSB and has an rms value of LSB/√12.
- An ideal ADC has SNR = 6.02N + 1.76 dB; ENOB measures what a real converter achieves.
- DNL and INL describe static accuracy and are set mainly by matching.
- Flash, SAR, pipeline and sigma-delta trade speed, resolution, power and area in different ways.