Chip Design path

Analog & Mixed-Signal Design

A free 10-lesson path through the analog side of a chip: the MOSFET as an amplifier, current mirrors and references, op-amps, noise and mismatch, data converters and PLLs, then the AMS design flow and how an analog block is handed to the digital SoC team.

10
lessons
Beginner to Intermediate
level
Free
every lesson
Start with lesson 1 →

Analog & Mixed-Signal Design

  1. 1What Analog and Mixed-Signal Design IsWhich analog blocks sit on a digital SoC, why they are designed differently, the analog trade-off octagon, and what the AMS engineer does.
  2. 2The MOSFET as an Analog DeviceRegions of operation, the square law, transconductance, output resistance, intrinsic gain and gm/ID sizing, with the small-signal model.
  3. 3Single-Stage AmplifiersCommon-source, source follower and common-gate stages, the cascode, and their gain and output resistance, with a worked numeric comparison.
  4. 4Current Mirrors and ReferencesBasic and cascode current mirrors, ratioing and output resistance, the bandgap reference built from PTAT and CTAT voltages, and the LDO block.
  5. 5Differential Pairs and Op-AmpsDifferential pairs, CMRR, the five-transistor OTA, two-stage op-amps, Miller compensation, gain-bandwidth and phase margin on a Bode plot.
  6. 6Noise, Mismatch and Analog LayoutThermal, flicker and kT/C noise, the Pelgrom mismatch law, and the layout techniques that manage them: common centroid, dummies and guard rings.
  7. 7Data ConvertersSampling, Nyquist and quantization, SNR = 6.02N + 1.76 dB, DNL, INL and ENOB, and the flash, SAR, pipeline and sigma-delta ADCs plus DAC basics.
  8. 8PLLs and Clock GenerationHow a charge-pump PLL multiplies a reference: PFD, charge pump, loop filter, VCO and divider, lock, jitter versus phase noise, and PD integration.
  9. 9The Analog Design FlowFrom specification to sign-off: schematic capture, Spectre analyses, PVT corners and Monte Carlo, layout, DRC and LVS, extraction and re-simulation.
  10. 10Integrating Analog into a Digital SoCAnalog hard macros on a digital SoC: abstract views, keep-outs, power domains and level shifters, shielded routing, AMS verification and handoff.