Noise, Mismatch and Analog Layout

Lessons 2 to 5 treated transistors as ideal, noiseless and perfectly matched. Real devices are none of these. Random motion of charge adds noise to every signal, and no two transistors drawn identically are ever exactly identical on silicon. These two effects set the floor on what any analog circuit can resolve – the smallest signal an ADC can detect, the offset of a comparator, the accuracy of a current mirror.

This lesson describes the main noise sources, the statistics of mismatch, and the layout techniques that analog layout engineers use to manage both. It is also the lesson that most directly explains why analog layout looks so different from a placed-and-routed digital block.

Reading time: about 9 minutes.

6.1 Thermal noise

Thermal noise comes from the random thermal motion of carriers in any resistive material. It is white – the same power at every frequency – and proportional to absolute temperature. For a resistor R, the open-circuit noise voltage has a power spectral density (PSD) of

vn² = 4·k·T·R      (V²/Hz)          (6.1)

A 1 kΩ resistor at 300 K therefore produces about 4.07 nV/√Hz. In a MOSFET in saturation, the channel produces a drain current noise of 4kTγgm, where γ is about 2/3 for long-channel devices and somewhat higher for short channels. Dividing by gm² refers this to the gate:

vn,in² = 4·k·T·γ / gm      (V²/Hz)          (6.2)

This is the expression lesson 1 used to show that halving the noise voltage costs four times the current. Thus, thermal noise is fundamentally a power problem: the only way to reduce it in a given device is to increase gm.

6.2 Flicker noise

Flicker noise, or 1/f noise, is associated with carriers being trapped and released at the interface between the channel and the gate oxide. Its PSD rises at low frequencies, and a common model refers it to the gate as

vn,in² = K / (Cox · W · L · f)          (6.3)

where K is a process-dependent constant. Flicker noise falls with gate area, not with current, so the designer reduces it by drawing larger input devices. In many processes PMOS devices show lower flicker noise than NMOS devices, which is one reason some low-frequency amplifiers use a PMOS input pair, though this varies by technology and should be checked against the process data.

Figure 6.1 shows the two together. The frequency at which flicker noise equals thermal noise is the corner frequency fc. Below it, flicker noise dominates; above it, thermal noise does.

Lowercase noise quantities are spectral densities. The total noise is found by integrating the PSD over the bandwidth of interest and taking the square root. Noise adds as power, not as voltage: two uncorrelated sources of 3 µV and 4 µV rms combine to 5 µV rms.

6.3 kT/C noise

Let us consider a switch with on-resistance R charging a capacitor C, as in the sample-and-hold of an ADC (lesson 7). The resistor's thermal noise is filtered by the RC network. Integrating 4kTR over the RC low-pass response gives a total noise power on the capacitor of

vn,rms² = k·T / C          (6.4)

Remarkably, R cancels. A larger resistance makes more noise per hertz but narrows the bandwidth by the same factor. When the switch opens, this noise is frozen onto the capacitor as a random sampling error.

Thus, the resolution of a sampled system sets a minimum capacitor size, which in turn sets the current needed to charge it quickly. Every additional bit of resolution needs four times the capacitance for the same kT/C margin.

6.4 Random mismatch and the Pelgrom law

Two transistors drawn identically, side by side, will differ slightly in threshold voltage and current factor, because the number and position of dopant atoms, the edge roughness and the oxide charge vary at random. Pelgrom and colleagues showed that the standard deviation of the difference falls with the square root of the device area:

σ(ΔVTH)  = AVT / √(W·L)          (6.5)
σ(Δβ/β)  = Aβ  / √(W·L)          (6.6)

AVT and Aβ are process constants published by the foundry. AVT is often quoted in mV·µm, and in many modern processes it is a few mV·µm.

This is the precision-against-area corner of the octagon from lesson 1. It also costs speed: larger devices bring more capacitance. Designers sometimes avoid the trade-off with circuit techniques such as offset calibration, auto-zeroing or chopping, at the cost of complexity.

6.5 Systematic mismatch

Random mismatch can only be reduced by area. Systematic mismatch, by contrast, comes from predictable effects and can be cancelled by layout:

• Gradients – oxide thickness, doping and temperature vary smoothly across the die. Two devices a few tens of microns apart see different values.
• Edge and etch effects – the outermost finger of a device sees a different environment from the inner ones, so it etches and stresses differently.
• Stress and well proximity – shallow trench isolation stress and the distance to the well edge shift VTH and mobility in advanced processes.
• Orientation – devices rotated relative to each other may behave differently because of the crystal and the implant angle.
• Asymmetric routing – unequal wire resistance in the source connection of two matched devices behaves like a VTH offset.

6.6 Matching layout techniques

Figure 6.2 shows the two arrangements most often used for matched pairs.

Table 6.1 summarizes what each technique addresses.

It is advisable to place matched devices close together, away from well edges and away from large heat sources such as output drivers, because even common-centroid layout only cancels the linear part of a gradient.

6.7 Guard rings, shielding and substrate coupling

On a mixed-signal SoC, the largest noise source is often not the transistor itself but the digital logic next to it. Each switching edge injects current into the shared substrate and onto the supplies, and that noise couples into analog nodes through junction capacitances and the body effect. This is substrate coupling. Three defences are standard:

1. Guard rings – a ring of p+ diffusion tied to ground around NMOS devices, or n+ in n-well tied to the supply around PMOS devices, collects stray carriers before they reach the protected circuit. Guard rings also help prevent latch-up. Deep n-well isolation, where the process offers it, separates the local p-well of sensitive NMOS devices from the main substrate.
2. Shielding – grounded metal lines on either side of a sensitive net, or a grounded plane on the layer below, give coupled charge a path to ground instead of into the signal.
3. Separation – distance, separate analog supply and ground pins, and separate power domains (lesson 10) keep digital switching currents off the analog rails.

Thus, much of what a PD engineer sees as "rules from the analog team" – keep-out zones, shielded nets, separate supplies – is the floorplan-level version of the techniques in this section. Lesson 10 shows how they are passed on.

6.8 Interview questions

What is the difference between thermal and flicker noise? Thermal noise is white and set by gm (4kTγ/gm at the gate). Flicker noise rises as 1/f and is set by gate area (K/(Cox·W·L·f)).

What is kT/C noise and why is it independent of R? It is the total thermal noise sampled onto a capacitor. A larger R raises the noise density but lowers the bandwidth by the same factor, so the integral is kT/C.

State the Pelgrom law. The standard deviation of VTH mismatch is AVT/√(W·L), so reducing it by a factor of two needs four times the area.

Why use common-centroid layout and dummies? Common centroid places matched devices at the same effective centre so linear gradients cancel; dummies give every active finger the same surroundings so edge effects cancel.

What does a guard ring do? It collects substrate carriers around a sensitive or noisy region, reducing substrate coupling and latch-up risk.