What Analog and Mixed-Signal Design Is | Analog & Mixed-Signal

A modern system-on-chip (SoC) is mostly digital by area, but it cannot work without a handful of analog circuits. Something has to generate the clock, convert real-world signals into numbers, regulate the supply, and drive signals off the chip. Analog and mixed-signal (AMS) design is the discipline that builds those circuits and places them on the same die as millions of standard cells.

This path is written for a reader who already knows digital design or physical design (PD) and wants to understand what happens on the analog side of the floorplan. We will build up from a single transistor to complete blocks, and finish with how those blocks are handed to the PD team.

Reading time: about 8 minutes.

1.1 Where analog lives on an SoC

Let us consider a typical application processor or microcontroller floorplan, shown in Figure 1.1. The digital core – CPU, memories, interconnect, peripherals – sits in the middle and takes most of the area. Around it, and usually close to the pads, sit the analog blocks:

PLL (phase-locked loop) – multiplies a low, clean reference such as a 25 MHz crystal into the GHz clocks the core needs. Lesson 8 covers it.
ADC and DAC (analog-to-digital and digital-to-analog converters) – translate between voltages and codes for audio, sensors, radio baseband and touch. Lesson 7 covers them.
LDO and bandgap – a low-dropout regulator produces a clean local supply, and a bandgap reference produces a voltage that barely moves with temperature or supply. Lesson 4 introduces both.
IO cells – drivers, receivers, ESD (electrostatic discharge) protection and level shifting between the core voltage and the pad voltage.
SerDes (serializer/deserializer) PHY – the high-speed link circuits behind PCIe, USB and Ethernet, with their own PLLs, equalizers and clock recovery.
Sensors – temperature sensors, voltage monitors and power-on reset circuits that tell the digital side what the silicon is experiencing.

Figure 1.1 A simplified SoC floorplan. The digital core takes most of the area, while the analog blocks (blue outline) sit at the periphery, close to the pads they talk to and away from the noisiest digital logic. Each analog block also has a digital interface into the core.

Thus, even a chip described as "digital" is a mixed-signal chip. The analog blocks are small, but each one sits on the critical path to the product working at all – a PLL that does not lock means no clock, and no clock means nothing else matters.

1.2 Why analog is designed differently

A digital gate has a remarkable property: it restores the signal. An input that is slightly degraded – a "1" at 0.9 V instead of 1.0 V – still produces a clean output, because the gate's high gain around the switching threshold pushes the output to a rail. Noise and small errors are discarded at every stage. That is why digital design can be automated: synthesis picks cells from a library, and static timing analysis only needs to know whether a transition arrives in time.

An analog circuit has no such margin. The signal is the voltage or current itself, and every millivolt of error travels to the output. Consequently:

Every device is sized by hand. There is no standard-cell library for an amplifier. The designer chooses each transistor's width, length and bias current against the specification.
Small effects matter. Thermal noise, threshold-voltage mismatch between two "identical" transistors, and a few femtofarads of wiring capacitance can each break a specification. Lesson 6 is devoted to these.
Layout is part of the circuit. The same schematic can work or fail depending on how its devices are placed and connected. Analog layout is therefore usually drawn by hand, or with heavy guidance, rather than placed and routed automatically.
Verification is by simulation. There is no analog equivalent of STA that proves correctness exhaustively. The designer simulates the circuit across process, voltage and temperature, as lesson 9 describes.

In other words, digital design trades raw efficiency for robustness and automation. Analog design spends the designer's time to get the efficiency back, one circuit at a time.

1.3 The analog design octagon

Every analog specification competes with the others. A widely used way to picture this is the analog design octagon, popularized by Razavi. Figure 1.2 shows a version with eight corners: gain, speed, power, noise, linearity, voltage swing, supply voltage and area. (Razavi's original lists input and output impedance where we have area. For a block that will be placed on an SoC, area is the more pressing concern.)

Figure 1.2 The analog design octagon. There is no single "best" amplifier, only the one whose position on these eight axes matches the specification. Notice that supply voltage and voltage swing sit next to each other: as supplies fall with each process node, the room for signal swing falls with them.

A few of the trade-offs appear in almost every block:

Noise against power. Lower noise needs a larger transconductance in the input transistor, which needs more current.
Gain against speed. High-gain stages tend to have high output resistance, which forms a slow pole with the load capacitance.
Precision against area. Random mismatch falls only with the square root of device area, so precise circuits need large devices (lesson 6).
Swing against supply. Each transistor stacked between the rails needs a few hundred millivolts to stay in saturation, which leaves less room for the signal at low supply voltages.

1.4 A trade-off in numbers

To make the noise-against-power trade-off concrete, let us work through one number. We will meet the transistor quantities used here properly in lesson 2 and lesson 6; for now, accept them as given.

Worked example

The thermal noise of a MOSFET input stage, referred to its gate, has a power spectral density of approximately 4kTγ/gm, where k is Boltzmann's constant, T the absolute temperature, γ a device factor and gm the transconductance.

Assuming T = 300 K, γ = 2/3 (the long-channel value) and gm = 1 mS:

4kTγ/gm = 4 × 1.38×10⁻²³ × 300 × 0.667 / 10⁻³ ≈ 1.10×10⁻¹⁷ V²/Hz, which is about 3.3 nV/√Hz.

Suppose the specification asks for half this noise voltage, about 1.66 nV/√Hz. Noise voltage density scales as 1/√gm, so gm must rise by a factor of four, to 4 mS. Assuming the transistor keeps the same overdrive voltage, gm is proportional to the drain current (lesson 2), so the current – and the power of that stage – also rises by a factor of four.

Thus, halving the noise voltage costs four times the power in this stage. Numbers like this are why the AMS engineer starts from the specification and pushes back when a requirement is tighter than the system needs.

1.5 The role of the AMS engineer

An AMS team usually contains three overlapping roles:

Circuit designer – turns a specification into a schematic, sizes the devices and proves the circuit by simulation across corners.
Layout engineer – draws the physical layout with matching, shielding and guard rings, and closes DRC and LVS (design rule check and layout versus schematic).
Mixed-signal verification engineer – builds behavioral models of the analog blocks and checks that they work together with the digital logic around them.

For a PD engineer, the AMS team is a supplier and a customer at once. It supplies hard macros with abstract views, and it expects the PD team to respect keep-out regions, supply connections and routing rules. Lesson 10 lists what must pass between the two teams. It is better to understand the analog side early, because most integration problems – a noisy supply, an unshielded reference net, a level shifter in the wrong place – are cheap to prevent at floorplan time and expensive to fix after routing.

1.6 How this path is organized

The lessons build on one another:

Lessons 2 to 5 cover the circuit building blocks: the transistor as an analog device, single-stage amplifiers, current mirrors and references, and differential pairs and op-amps.
Lesson 6 covers the physical limits – noise and mismatch – and the layout techniques that manage them.
Lessons 7 and 8 describe the two system blocks a PD engineer meets most often: data converters and PLLs.
Lessons 9 and 10 describe the design flow and the integration of analog macros into a digital SoC.

Formulas are kept to the textbook level and introduced in words first. Unless otherwise mentioned, transistors are assumed to be in saturation, and numbers use a generic process rather than a specific foundry node.

1.7 Interview questions

Name four analog blocks found on a typical digital SoC and what each does. A PLL generates high-frequency clocks from a reference, an ADC converts sensor or audio voltages into codes, an LDO produces a clean regulated supply, and a bandgap provides a temperature-stable reference voltage. IO cells and SerDes PHYs are also analog-heavy.

Why can digital design be automated more easily than analog design? Digital gates restore the signal at every stage, so correctness reduces to logic function plus timing, which libraries and STA can capture. Analog circuits carry information in exact voltages and currents, so device sizing, noise, mismatch and layout parasitics all affect the result directly.

What is the analog design octagon? A picture of eight competing specifications – for example gain, speed, power, noise, linearity, swing, supply voltage and area – showing that improving one usually degrades another.

How much does halving the thermal noise voltage of an input stage cost in power? Roughly four times, because noise voltage scales as 1/√gm and, at constant overdrive, gm scales with current.

Key takeaways

Every SoC contains analog blocks: PLLs, data converters, regulators and references, IO, SerDes and sensors.
Digital logic restores signals at every gate; analog circuits do not, so every error reaches the output.
Analog design is a negotiation between gain, speed, power, noise, linearity, swing, supply and area.
Analog layout is part of the circuit, which is why analog blocks arrive at PD as hand-built hard macros.
The AMS and PD teams depend on each other, and lesson 10 describes the handoff between them.