Chip Design path

CAD & Methodology

A free 10-lesson path into the flow behind every chip: the RTL-to-GDS stages and their handoff files, flow scripting in Tcl and Python, Makefiles, PDKs and design data, compute farms, QoR reporting, regressions and CI, signoff criteria, and a small open-source flow built end to end.

10
lessons
Beginner to Intermediate
level
Free
every lesson
Start with lesson 1 →

CAD & Methodology

  1. 1What CAD and Methodology Engineers DoThe CAD and methodology role explained: flow owner, tool expert and infrastructure, what flows and methodologies are, and how the work differs from design.
  2. 2Anatomy of an RTL-to-GDS FlowThe RTL-to-GDS flow stage by stage, from synthesis to signoff, with the files handed between stages: netlist, SDC, UPF, LEF, LIB, DEF, SPEF and GDS.
  3. 3Flow Scripting with Tcl and PythonTcl as the tool control language, keeping configuration apart from scripts, and a Python wrapper that generates Tcl, runs a tool and checks logs and exit codes.
  4. 4Makefiles and Flow DependenciesHow make targets, prerequisites and timestamps drive incremental reruns, with phony targets and a small Makefile for a syn, place, route and STA flow.
  5. 5PDKs, Libraries and Design Data ManagementWhat a PDK contains, the library views of a standard cell, version control for design data with git, git LFS or DM tools, and directory and run conventions.
  6. 6Running Jobs on a Compute FarmBatch schedulers such as LSF and SLURM, queues, core and memory requests, licences as a shared resource, and running timing corners in parallel on a farm.
  7. 7QoR Metrics and ReportingExtracting WNS, TNS, area, utilisation, power and DRC counts from tool reports with a regex script, then building QoR tables and tracking trends across runs.
  8. 8Regression and Continuous IntegrationNightly flow regressions, comparing results against a golden reference, CI pipelines at concept level, choosing what to gate on, and handling flaky runs.
  9. 9Methodology Checks and Signoff CriteriaSanity checks at each flow stage, a signoff checklist covering timing, IR drop, EM, DRC, LVS and antenna, and how waivers are reviewed, recorded and governed.
  10. 10Building a Mini Flow End to EndA small open-source RTL-to-GDS flow with Yosys and OpenROAD: directory layout, config file, stage scripts, a Makefile and a QoR summary tying the path together.