Physical Design Engineer

What the job is

A physical design engineer turns the synthesized netlist into a real layout. Your inputs are the netlist, SDC constraints, and LEF and Liberty libraries. You build the block through floorplan, power plan, placement, clock tree synthesis, routing and signoff. The output is a GDSII or OASIS file the fab can build.

PD sits after synthesis and before tapeout. It is where timing, power, area and manufacturability all meet. A block can be logically perfect and still fail because of congestion, IR drop, crosstalk or a hold violation across one corner.

The job is half engineering judgment and half automation. You read timing and congestion reports, decide what to change, and drive tools like Innovus or ICC2 with Tcl scripts. Every day is a closure problem with numbers attached.

Skill ladder

Three stages, in order. Each ends with something you can show, not just something you studied.

1. Foundation4-6 months

   Skills

   • Digital logic, CMOS inverter, delay and power basics
   • Setup and hold equations, slack, clock skew
   • The full flow: synthesis, floorplan, powerplan, place, CTS, route, signoff
   • Input files: Verilog netlist, SDC, LEF, Liberty (.lib), DEF, GDS
   • Linux shell, Tcl basics and reading reports
   • Standard cells, rows, sites and metal layers

   Tools

   OpenLaneOpenROADKLayoutYosysOpenSTA

   You are here when: You ran a small design, such as a 5-stage CPU, through OpenLane on SKY130 to a DRC- and LVS-clean GDS. You can explain each stage's report.

2. Job-ready6-9 months more

   Skills

   • Floorplan: aspect ratio, core utilization, macro placement, halos, blockages, pin placement
   • Power planning: rings, straps, rails, IR drop basics and EM awareness
   • Placement: density, congestion, timing-driven placement, scan chain reordering
   • CTS: skew, latency, insertion delay, NDRs, clock gating cells
   • Routing: global and detail route, DRC types, antenna fixes, crosstalk basics
   • Timing closure: setup fixes, hold fixes, ECOs, MMMC views
   • Tcl scripting to automate flows and parse reports

   Tools

   Innovus or ICC2 (training or lab access)OpenROAD with OpenSTAMagic and NetgenKLayoutPython

   You are here when: You can explain every decision in your own RTL-to-GDS run. A QoR table shows WNS, TNS, utilization, skew, DRC and power before and after your changes.

3. Senior5-8 years on the job

   Skills

   • Owning a full block or subsystem from netlist to signoff
   • Hierarchical flows, partitioning, budgeting and top-level integration
   • Low-power implementation with UPF: power domains, isolation, level shifters, power switches
   • Advanced CTS: multi-source CTS, clock mesh awareness, useful skew strategy
   • IR/EM signoff and fixing dynamic IR drop
   • Advanced-node rules: double patterning, via pillars and density rules
   • Estimating schedules and mentoring juniors

   Tools

   Innovus or Fusion Compiler / ICC2Tempus or PrimeTimeVoltusCalibreQuantus or StarRC

   You are here when: You have taken several blocks to tapeout as owner, and other engineers come to you to debug closure problems.

Learning path

1. Digital electronicsFlip-flops, setup and hold, and CMOS basics. Every PD interview starts here.
2. Verilog and synthesisKnow what a netlist is and how synthesis maps RTL to standard cells.
3. Tcl for EDAInnovus, ICC2 and OpenROAD are all driven by Tcl. Learn it early.
4. Physical design basicsFloorplan, powerplan, placement, CTS and routing explained step by step.
5. Run an open-source flow yourselfTake a small design to GDS on SKY130 with OpenLane or OpenROAD and read every report.
6. STA and constraintsLearn SDC, slack, clocks and exceptions. PD closure is timing closure.
7. Design planningMacro placement, channels, pin planning and power grid decisions in depth.
8. Innovus PnR mentor guideThe industry flow chapter by chapter, with real commands and checks.
9. PD interview sprintTimed questions on floorplan, CTS, routing, ECO and timing fixes.

Projects that prove it

• Physical design · Intermediate · 6-10 weeksTiny Tapeout Chip with OpenLaneTake a small design of your own from RTL to a GDS that passes precheck and goes on a real shared shuttle.
• Physical design · Intermediate · 6-8 weeksRTL-to-GDSII Implementation of a RISC-V CPUTake a small RISC-V core from RTL to a DRC- and LVS-clean GDSII on SKY130 with OpenLane and sign off timing across corners.
• Physical design · Intermediate · 4-6 weeksClock Tree Synthesis Study and Skew OptimizationRun clock tree synthesis with different buffers, fanout limits and sink clustering, and measure how each choice changes skew, latency and clock power.

More: Physical design projects

What interviews test

• Inputs and outputs of each PnR stage, and which files you need (netlist, SDC, LEF, .lib, tech file, RC corners)
• Floorplanning: core utilization, macro placement rules, channels, halos and blockages
• Power planning: rings, straps, rails, static vs dynamic IR drop, and EM
• Placement: congestion causes and fixes, density screens, timing-driven placement
• CTS: skew vs latency, insertion delay, NDRs, why clock nets get shielding or double spacing
• Setup vs hold fixing: which stage, which techniques, and why hold is fixed after CTS
• Crosstalk: delta delay vs glitch, aggressor and victim, fixes
• Antenna effect and its fixes: jumpers, diodes
• MMMC: why setup is usually worst at slow corners and hold at fast corners
• ECO flow and a Tcl scripting question on parsing a report

Mistakes freshers make

• Running OpenLane with default settings and calling it a project, so change one knob at a time and explain the QoR impact.
• Learning tool menus before STA, so master setup, hold and slack first because every PD decision is a timing decision.
• Memorizing CTS answers without numbers, so be able to say what skew and insertion delay your own run achieved.
• Avoiding Tcl and using only the GUI, so script one full stage and one report parser yourself.

Are you ready to apply?

Tick what you can already do. Your ticks stay in this browser only.

Pay in India

Compare all roles and read the caveats