Anatomy of an RTL-to-GDS Flow

Every flow script, Makefile target and QoR table in this path refers to some stage of the RTL-to-GDS flow and to some file that stage reads or writes. Before writing any automation, it is therefore worth knowing the flow as a map: which stages exist, in what order, and what passes between them.

This lesson draws that map. It walks through the stages from synthesis to signoff, then lists the files handed from one stage to the next, and shows how a change at one stage propagates downstream. Lesson 4 turns exactly this map into Makefile dependencies, and lesson 10 implements a small version of it.

Reading time: about 8 minutes.

2.1 The flow as a chain of transformations

Let us consider the flow as a chain. Each stage reads one representation of the design, transforms it, and writes another. Synthesis turns behaviour into gates. Placement turns a list of gates into gates with coordinates. Routing turns coordinates into metal shapes. The final output, GDS, is nothing more than polygons on layers, which is what the foundry needs to make masks.

Two kinds of input travel alongside the design through the whole chain. The first is the library and technology data – cell timing in Liberty, cell and layer abstracts in LEF, rule decks for verification. The second is the design intent – timing constraints in SDC and power intent in UPF. These do not change from stage to stage in the way the design does, but every stage reads them.

2.2 The stages

Synthesis

Synthesis reads RTL, the SDC constraints, and the Liberty timing libraries. It maps the logic onto standard cells from the library and optimises for the timing, area and power targets. The output is a gate-level netlist in Verilog, together with a constraint file written back out for the next stage. Many flows also read physical data (LEF and a floorplan) at this point so that the tool can estimate wire delay better – this is usually called physically aware synthesis.

DFT insertion

Design-for-test (DFT) replaces ordinary flip-flops with scan flip-flops and stitches them into scan chains, so that the manufactured chip can be tested. It might also add test compression logic and memory built-in self-test. Besides a modified netlist, the DFT step usually writes a scan definition file (often called scan DEF) that lets the placement tool reorder chains according to physical location.

Floorplan

The floorplan sets the die and core size, places macros and IO pins, and builds the power grid. In a low-power design, the power domains described in UPF become physical regions here. The output is the first physical database of the design.

Placement

Placement assigns a legal location to every standard cell, then optimises timing using estimated wire lengths. Scan chains are reordered here using the scan DEF.

Clock tree synthesis

Before CTS, the clock is treated as ideal. CTS builds a buffered tree from the clock source to every register clock pin, balancing skew within the targets. After CTS, timing uses real clock arrival times, and hold fixing usually starts here.

Routing

Global routing assigns nets to regions, and detailed routing draws actual wires and vias on the metal layers obeying the design rules in the technology LEF. Post-route optimisation then fixes the timing that real wires have changed.

Extraction and STA

An extraction tool computes the resistance and capacitance of every routed net and writes them in SPEF. The signoff STA tool reads the netlist, libraries, SDC and SPEF, and checks setup, hold and design rules at every required corner and mode. It might also write SDF for gate-level simulation.

Physical verification and signoff

The layout is exported as GDSII or OASIS, and a physical verification tool runs DRC (design rules), LVS (layout matches netlist), antenna and other checks using the foundry's rule decks. Signoff is the decision, recorded against a checklist, that every criterion is met. Lesson 9 describes those criteria.

2.3 The files handed between stages

The table lists the main formats. Lesson 5 explains where the library files come from; here the point is which stage produces and which consumes each one.

A useful habit is to read each row as a contract. If placement expects a netlist and an SDC, the flow should check that both exist and are newer than their sources before placement starts. That habit is the basis of lesson 4.

2.4 Exchange formats and native databases

Between two stages run in the same tool, flows usually save the tool's native database rather than DEF and Verilog. The native database keeps everything – timing settings, routing guides, attributes – and loads faster. Between different tools, or for archiving, flows write the open exchange formats, because those can be read by any tool.

Thus, a typical flow saves a native database after each PnR stage and writes DEF, Verilog and SPEF only at hand-off points: to the signoff STA tool, to the extraction tool, and to the verification tool. It is better to keep this distinction explicit in the flow, because a DEF round-trip can lose information that the native database carries.

2.5 Tracing a change through the flow

Let us consider what reruns when something changes. The answer depends upon where in the chain the change enters.

One case needs care. A library or SDC change enters every stage at once, since every stage reads them. In such a case, a complete rerun is usually required, even though the design itself did not change.

2.6 Interview questions

What is the difference between LEF and Liberty? LEF is a physical abstract: layers and vias in the technology LEF, and cell size, pin shapes and blockages in the cell LEF. Liberty is a timing and power model: delay tables, setup and hold constraints, pin capacitance and leakage, per PVT corner. Placement needs both; signoff STA needs Liberty but not LEF.

Why does a flow save a native database between PnR stages instead of DEF? The native database holds every setting and attribute the tool uses and loads faster. DEF is an exchange format and might not carry everything, so it is used where data has to cross to another tool.

What does SPEF contain and who reads it? Extracted resistance and capacitance (and optionally coupling capacitance) per net. It is read by signoff STA, power analysis and IR drop analysis.

If only the SDC changes, which stages must rerun? Every stage that reads it and every stage after the first one that does. Since synthesis reads SDC, a timing-relevant SDC change usually means rerunning the whole flow, although a pure reporting change at STA might need only an STA rerun.