Design Verification Engineer

What the job is

A verification engineer tries to break the design before it becomes silicon. You read the spec, plan what must be tested, build a testbench, write tests and measure coverage until the team is confident.

Verification runs in parallel with RTL design and often takes more effort than the design itself. That is why it is the largest hiring area for freshers in India.

The work is part hardware and part software. You write object-oriented SystemVerilog, use UVM, write assertions and automate regressions with Python or shell.

Skill ladder

Three stages, in order. Each ends with something you can show, not just something you studied.

1. Foundation3-6 months

   Skills

   • Digital logic, FSMs, setup and hold
   • Verilog RTL and directed testbenches
   • SystemVerilog data types, arrays, queues
   • OOP in SystemVerilog: classes, inheritance, polymorphism
   • Linux, git and Python scripting

   Tools

   Icarus VerilogVerilatorGTKWavecocotb

   You are here when: You have a class-based SystemVerilog testbench for a FIFO with a scoreboard and random stimulus.

2. Job-ready6-9 months more

   Skills

   • Constrained randomization and functional coverage
   • UVM: agents, sequences, drivers, monitors, scoreboards, factory, config_db
   • SystemVerilog Assertions: sequences, properties, implication
   • Writing a verification plan from a spec
   • Protocols: UART, SPI, I2C, APB, AXI4-Lite
   • Regression scripting and result summaries

   Tools

   Questa, VCS or Xcelium (via training or labs)EDA Playground for UVM practicecocotb with VerilatorPython

   You are here when: A UVM environment for an AXI4-Lite or UART design with coverage closure above a target such as 95%, documented on GitHub.

3. Senior5-8 years on the job

   Skills

   • Owning test plans for a full IP or subsystem
   • Verification IP architecture and reuse
   • Formal verification for control logic
   • Gate-level and low-power (UPF) simulation
   • Coverage strategy and signoff criteria
   • Mentoring and estimation

   Tools

   VCS, Xcelium or QuestaJasperGold or VC FormalVerdi or SimVision debuggersPython regression frameworks

   You are here when: You signed off verification for an IP that taped out with no escapes to silicon.

Learning path

1. Digital electronicsVerification starts with knowing what correct hardware looks like.
2. VerilogRead and write RTL so you can debug the design you test.
3. Python-based testbenchescocotb lets you start testing with Python and Verilator for free.
4. SystemVerilog OOPClasses, randomization and coverage before touching UVM.
5. UVM step by stepFIFO, then UART, then AXI4-Lite, each with scoreboard and coverage.
6. AssertionsWrite SVA for handshake and protocol rules on your own designs.
7. One deep projectA full UVM environment with a verification plan and coverage report.
8. Interview practiceDigital logic, SystemVerilog, UVM phases and debug scenarios.

Projects that prove it

• Verification · Intermediate · 4-6 weeksSVA Assertion Library for APB, AXI4-Lite and FIFOsA reusable, parameterized SystemVerilog Assertions library that you bind to any design to check common protocols and structures.
• Verification · Intermediate · 6-8 weeksEthernet MAC Verification in UVMA UVM environment for a 1 Gb/s Ethernet MAC that checks framing, CRC-32, padding, pause frames and error handling.
• Verification · Intermediate · 8-10 weeksAXI4 Verification IP (Master, Slave and Monitor)A reusable AXI4 VIP with master and slave agents, a protocol checker and coverage, usable in any UVM testbench.

More: Verification projects · RTL design projects

What interviews test

• SystemVerilog OOP: virtual methods, polymorphism, shallow vs deep copy
• Constraints: solve-before, dist, inline constraints, randc
• UVM phases and the objection mechanism
• UVM factory overrides and config_db
• Sequence, sequencer and driver handshake
• Functional vs code coverage, and covergroups with cross coverage
• Writing SVA for a req/ack handshake
• Mailboxes, semaphores and fork-join variants
• Write a verification plan for a FIFO or UART on the spot
• Digital logic and Verilog basics

Mistakes freshers make

• Jumping into UVM without SystemVerilog OOP, so learn classes and randomization first.
• Treating 100% code coverage as done, so write a functional coverage model from the spec.
• Copying a UVM template without understanding phases, so build one agent from scratch and explain it.
• Ignoring the design, so read the RTL of your DUT and know its corner cases.

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