DFT Engineer

What the job is

A design-for-test engineer adds logic so every manufactured chip can be tested quickly. You insert scan chains, generate ATPG patterns, add memory BIST and connect it all through JTAG. Without DFT, bad parts would reach customers.

DFT sits between synthesis and physical design, with handoffs to the test and product engineering teams. Your decisions affect area, timing, test time and the cost of every part shipped.

The role mixes digital design, fault models and tool flows. You care about test coverage numbers, scan shift timing and how patterns behave on a real tester.

Skill ladder

Three stages, in order. Each ends with something you can show, not just something you studied.

1. Foundation3-5 months

   Skills

   • Digital logic, flip-flops and timing basics
   • Fault models: stuck-at, transition, bridging
   • Controllability and observability
   • Scan flip-flops, scan chains, shift and capture
   • Verilog and gate-level netlists
   • Tcl and Linux basics

   Tools

   YosysIcarus VerilogFault (open-source DFT)Python

   You are here when: You wrote a small stuck-at fault simulator in Python and inserted scan into a counter design, then explained shift and capture waveforms.

2. Job-ready6-9 months more

   Skills

   • Scan insertion rules, scan DRC, lockup latches, chain balancing
   • ATPG for stuck-at and transition (launch-on-shift, launch-on-capture)
   • Test compression concepts
   • MBIST algorithms such as March C-
   • JTAG IEEE 1149.1 TAP state machine
   • At-speed test and OCC basics
   • Gate-level simulation of patterns

   Tools

   Tessent, TestMAX or Modus (training or lab)FaultVerilator or IcarusTcl and Python

   You are here when: You inserted scan, ran ATPG and reported coverage with a list of untestable faults and why.

3. Senior5-8 years on the job

   Skills

   • Chip-level DFT architecture and test-time planning
   • Hierarchical DFT and IEEE 1687 / 1500 concepts
   • Memory repair and BISR
   • Low-power test and power-aware ATPG
   • Silicon bring-up and diagnosis with test engineering

   Tools

   TessentTestMAXModusPrimeTime for DFT timing

   You are here when: You owned DFT for a chip that met its coverage and test-time targets in production.

Learning path

1. Digital electronicsFlip-flops, FSMs and timing are the base of scan and ATPG.
2. VerilogRead netlists and write small test logic with confidence.
3. SynthesisScan insertion happens around synthesis. Know what a netlist contains.
4. Tcl for EDADFT tools are scripted in Tcl.
5. Fault models and scanLearn stuck-at and transition faults, then build a scan chain by hand.
6. STA basicsScan shift and at-speed capture are timing problems too.
7. Build DFT projectsA fault simulator, a JTAG TAP and an MBIST controller.
8. Interview practiceDigital logic, scan, ATPG coverage and timing questions.

Projects that prove it

• DFT & test · Intermediate · 4-6 weeksBit-Parallel Stuck-At Fault SimulatorWrite a fault simulator for ISCAS'85 circuits that grades test vectors and shows how coverage grows with patterns.
• DFT & test · Beginner · 4-6 weeksIEEE 1149.1 Boundary Scan (JTAG) TAPImplement a standard JTAG TAP controller with boundary-scan cells, IDCODE and a BSDL file, then test it on an FPGA.
• DFT & test · Beginner · 5-7 weeksMarch C- MBIST ControllerDesign a memory BIST controller that runs March C- on an SRAM, flags failures and logs the failing address.

More: DFT & test projects

What interviews test

• Stuck-at vs transition fault models
• Scan flip-flop structure and shift vs capture mode
• Why lockup latches are used between clock domains in a scan chain
• Test coverage vs fault coverage
• Launch-on-shift vs launch-on-capture
• Why ATPG coverage stalls and how test points help
• MBIST March algorithms
• JTAG TAP controller states and instructions
• Scan shift timing: hold issues and shift frequency
• Test compression basics

Mistakes freshers make

• Learning tool commands without fault models, so start with stuck-at faults on a paper circuit.
• Ignoring timing, so study why scan shift creates hold problems and how lockup latches help.
• Treating DFT as a tool button, so build a small scan chain and JTAG TAP in Verilog yourself.
• Applying only to DFT openings, so also apply to PD and DV roles, since engineers often move into DFT later.

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