The single-port 6T SRAM of lessons 4 to 6 is the most common on-chip memory, but it is not the only one. Processors need register files that can be read and written by several instructions in the same cycle. Network chips need memories that search by content instead of by address. Boot code needs a memory that never changes, and configuration bits must survive power-off. Each of these needs has led to a different cell and a different array.
This lesson surveys these memories at the concept level: multi-port register files and the 8T cell, CAM and TCAM, ROM, DRAM and embedded DRAM, and the main non-volatile options. The aim is to know what each one is, how it differs from the 6T SRAM, and when a designer would choose it.
Reading time: about 9 minutes.
7.1 Register files and multiple ports
A register file is a small, fast memory, typically tens to a few hundred words, that sits inside a processor pipeline. A simple processor reads two source operands and writes one result per instruction, so its register file needs two read ports and one write port, often written 2R1W. A processor that issues several instructions per cycle needs proportionally more ports.
Each port needs its own wordline in every row and its own bitline (or bitline pair) in every column, because each port can address a different word in the same cycle. Adding a port therefore makes the cell both wider and taller. Roughly, the cell area grows with the square of the number of ports, which is why register files with many ports are expensive and why architects work hard to limit port count.
Register files are built in three ways, depending on size and speed.
- Synthesized from flip-flops or latches โ practical for small files, easy to integrate, but large and power-hungry per bit.
- Compiled register-file macros โ many memory compilers (lesson 8) offer "two-port" register files with one read and one write port, usually built on an 8T cell.
- Custom multi-port arrays โ used in high-performance processor cores, with cells and periphery designed for the exact port count.
7.2 The 8T cell
The 8T cell adds a two-transistor read port to the 6T cell. Let us consider Fig. 7.1. The 6T core is written exactly as in lesson 4, through the write wordline WWL and the write bitlines WBL and WBLB. Reading uses a separate read wordline RWL and a single read bitline RBL.
For a read, RBL is precharged high and RWL is raised. If QB is high, M8 conducts and RBL discharges through M7 and M8. If QB is low, M8 is off and RBL stays high. Thus, RBL carries the value of Q, inverted, and it is sensed single-ended, often by a simple inverter or a skewed gate after a larger swing.
The key advantage is that the read current does not flow through the storage node. The read disturb of lesson 4 disappears, and the read static noise margin becomes equal to the hold margin. The designer can then size the 6T core for writability and the read stack for speed, without the conflict described in lesson 4. The 8T cell also gives a natural 1R1W register file, since a read and a write to different rows can occur in the same cycle.
The cost is area โ two extra transistors, an extra wordline and an extra bitline โ and a single-ended read that needs more swing than a differential one. In practice, 8T cells are used for register files and for low-voltage memories where read stability would otherwise limit the minimum supply.
7.3 CAM and TCAM
A normal memory takes an address and returns data. A content-addressable memory (CAM) does the reverse: it takes a data word, called the search key, and returns the addresses of the entries that match it. Each CAM cell contains storage and a small comparison circuit. All the cells of one entry share a matchline, which is precharged high; any bit that mismatches the key discharges it. After a search, the matchlines that remain high mark the matching entries, and a priority encoder reports the first one.
A ternary CAM (TCAM) stores three states per bit: 0, 1 and X (don't care). An X matches either key value. This makes TCAM ideal for the longest-prefix match in network routers, where a routing entry specifies only the leading bits of an address. CAMs are also used for translation lookaside buffers and fully associative cache tags.
Because every entry is compared on every search, CAMs draw much more power per bit than SRAM, and each cell is considerably larger. Hence, they are used only where a parallel search is essential.
7.4 ROM
A read-only memory (ROM) has its contents fixed during manufacture. In a NOR-type ROM, each cell position either contains a transistor connecting the bitline to ground or does not, and the presence or absence is set by one mask layer, typically a contact or via. When the wordline is raised, bitlines with a transistor discharge and the others stay high. ROMs are very dense and robust, and are used for boot code, microcode and fixed lookup tables. The obvious limitation is that a content change requires a mask change, so code that might need a fix is usually placed in a writable memory, with only a minimal boot loader in ROM.
7.5 DRAM and embedded DRAM
A dynamic RAM (DRAM) cell is a single access transistor and a capacitor, the 1T1C cell. The bit is stored as charge on the capacitor. Let us consider Fig. 7.2.
Before a read, the bitline is precharged to VDD/2. When the wordline rises, the storage node and the bitline share their charge. The resulting change on the bitline is:
dV = (V_cell - VDD/2) x Cs / (Cs + C_BL) (7.1)
## For a stored 1, V_cell = VDD; for a stored 0, V_cell = 0Assuming VDD = 1.0 V, Cs = 25 fF and C_BL = 100 fF, a stored 1 gives dV = 0.5 x 25 / 125 = 0.10 V, and a stored 0 gives -0.10 V. A sense amplifier compares the bitline with a reference at VDD/2 and resolves this 100 mV signal. Notice that the capacitor has now lost its full level: the read is destructive, and the sense amplifier must write the value back. If C_BL were doubled to 200 fF, dV would fall to 0.5 x 25 / 225 = 56 mV, which is why DRAM bitlines are kept short.
The stored charge also leaks away over time, so every cell must be read and rewritten periodically. This is called refresh. Refresh costs power and occupies the memory for some of its time, but the 1T1C cell is far smaller than a 6T cell, so commodity DRAM offers much higher density.
Embedded DRAM (eDRAM) builds 1T1C cells inside a logic process, using a trench or a metal-insulator-metal capacitor. It gives a few times the density of SRAM on the same die, at the cost of extra process steps, refresh and slower access. It has been used for large last-level caches, for example the L3 cache of IBM's POWER7 processor.
7.6 Non-volatile memories
All of the memories above, except ROM, lose their data when the power is removed. Several non-volatile options exist on chip.
- Embedded flash stores charge on a floating gate or in a charge-trap layer. It is rewritable many times and is common in microcontrollers for program storage. It needs extra masks and high programming voltages, and it is not available in every advanced logic node.
- One-time programmable (OTP) memory, often built on antifuses, is programmed once by deliberately breaking down a thin oxide to create a conducting path.
- eFuses are small metal or polysilicon links that are blown by a programming current, typically through electromigration. They provide a few hundred to a few thousand bits for chip identification, analog trimming, configuration, and the memory-repair information of lesson 10.
- Emerging embedded memories such as magnetic RAM (MRAM) and resistive RAM (RRAM) store data as a resistance state. They are increasingly offered as embedded non-volatile options in some processes.
7.7 Choosing a memory
Table 7.1 summarizes when each memory is typically used.
| Memory | Key property | Typical use |
|---|---|---|
| 6T SRAM | Dense, fast, static, single port | Caches, buffers, scratchpads |
| 8T / multi-port RF | Decoupled read, several ports | Register files, low-voltage arrays |
| CAM / TCAM | Parallel search by content | Routing tables, TLBs, associative tags |
| ROM | Fixed at manufacture, very dense | Boot code, microcode, tables |
| eDRAM | Denser than SRAM, needs refresh | Large last-level caches |
| Flash, OTP, eFuse | Non-volatile | Firmware, trimming, IDs, repair data |
7.8 Interview questions
Why does an 8T cell have better read stability than a 6T cell? Its read path uses separate transistors whose gate is driven by the storage node, so read current never flows through the storage node and the read SNM equals the hold SNM.
Why does register-file area grow quickly with port count? Each port adds a wordline per row and a bitline per column, so the cell grows in both dimensions, roughly with the square of the number of ports.
What is the difference between a CAM and a TCAM? A CAM cell stores 0 or 1; a TCAM cell also stores X (don't care), which matches either value and allows prefix matching.
Why is a DRAM read destructive, and why is refresh needed? Charge sharing with the bitline disturbs the stored level, so it must be written back; and the stored charge leaks away, so it must be restored periodically.
Key takeaways
- Multi-port register files add a wordline and bitline per port, so area rises steeply with port count.
- The 8T cell decouples the read path, removing read disturb at the cost of area and a single-ended read.
- CAM and TCAM search all entries in parallel; TCAM's don't-care state suits prefix matching but costs area and power.
- DRAM and eDRAM use a 1T1C cell with charge sharing, destructive read and refresh in exchange for density.
- ROM, flash, OTP and eFuse provide non-volatile storage, with eFuses commonly holding memory-repair data.