Chip Design path

Custom & Memory Design

A free 10-lesson path into the blocks a standard-cell flow does not build for you: the CMOS inverter and sizing, standard-cell layout, the 6T SRAM bitcell, array architecture and periphery, register files and other memories, memory compilers, characterization and memory test.

10
lessons
Beginner to Intermediate
level
Free
every lesson
Start with lesson 1 →

Custom & Memory Design

  1. 1What Custom and Memory Design IsHow full-custom, semi-custom and standard-cell design differ, where custom work still matters, and how memories appear in a PD floorplan as hard macros.
  2. 2The CMOS Inverter and Transistor SizingThe inverter transfer curve, switching threshold, noise margins and beta ratio, how delay changes with size, and logical effort with the FO4 delay.
  3. 3Standard Cell DesignHow standard cells are built: rails, rows and track height, inverter and NAND2 layout, pin access, DRC-clean abutment and what a library contains.
  4. 4The 6T SRAM BitcellHow the 6T bitcell holds, reads and writes, why cell ratio and pull-up ratio conflict, the butterfly curve and SNM, and why bitcells use push rules.
  5. 5SRAM Array ArchitectureHow bitcells form an array of wordlines and bitline pairs, why column multiplexing and banking are used, and how a 2048x64 macro is organised.
  6. 6SRAM Periphery and TimingRow decoders with predecoding, precharge, latch-type sense amplifiers, write drivers, replica-bitline self-timing and the read timing of an SRAM.
  7. 7Register Files and Other MemoriesMulti-port register files and the 8T cell, CAM and TCAM, ROM, 1T1C DRAM and eDRAM, and on-chip non-volatile memory, with when each is used.
  8. 8Memory Compilers and Their ViewsWhat a memory compiler takes and produces, how to choose the mux factor for a floorplan, and the rules for placing memory macros in physical design.
  9. 9Characterization and LibertyHow cells and memories are characterized into Liberty: NLDM tables and interpolation, setup and hold arcs, power tables, memory timing arcs and corners.
  10. 10Memory Test, Repair and ReliabilityMBIST and memory fault models, the March C- algorithm, redundancy and repair, SECDED ECC, soft errors and low-voltage data retention.