SRAM Array Architecture

A single bitcell, as described in lesson 4, stores one bit. A memory macro arranges thousands or millions of them in a rectangular array, shares wires between them, and adds circuits to select one word at a time. How the cells are arranged – how many rows, how many columns, how many banks – decides the speed, power and shape of the macro.

This lesson builds the array step by step and works through one concrete case: a 2048-word by 64-bit SRAM. The choice we make here, the column multiplexing factor, reappears in lesson 8 as one of the main inputs to a memory compiler.

Reading time: about 8 minutes.

5.1 Rows, columns, wordlines and bitlines

Let us consider a memory of N words, each M bits wide. The simplest arrangement puts one word in each row: N rows and M columns. Every cell in a row shares one wordline, which connects to the gates of its access transistors. Every cell in a column shares one bitline pair, BL and BLB, which connects to the access transistor drains.

A read then proceeds as follows. The address is decoded and exactly one wordline is raised. Every cell on that row connects to its own bitline pair and begins to discharge one side. At the bottom of each column, a sense amplifier detects which side is falling. Writing is similar, except that write drivers force the bitlines before the wordline rises. Figure 5.1 shows the blocks involved.

5.2 Why one word per row does not work

For our 2048 x 64 memory, one word per row would give 2048 rows and 64 columns. Two problems appear immediately.

• Bitline load. Each bitline is connected to the drain of one access transistor in every row. With 2048 rows, the bitline carries 2048 drain capacitances plus a very long wire. A single bitcell has a small read current, so discharging this capacitance by even a hundred millivolts takes a long time.
• Shape. Bitcells are usually wider than they are tall, but not 32 times wider. An array of 2048 rows and 64 columns is a long, thin strip – in our worked example below it is 16 times taller than it is wide. Such a macro is very hard to place in a floorplan, as lesson 8 discusses.

Thus, the array must be folded: fewer rows, more columns.

5.3 Column multiplexing

With column multiplexing, each physical row holds several words side by side. If the mux factor is CM, each row holds CM words, and the array has:

rows          = N / CM
columns       = M x CM                              (5.1)
row bits      = log2(N / CM)
column bits   = log2(CM)

The words are not stored as contiguous blocks. They are interleaved: bit 0 of word 0, bit 0 of word 1, bit 0 of word 2, bit 0 of word 3, then bit 1 of word 0, and so on. The low address bits drive a column multiplexer that selects one column out of every CM for each output bit. This arrangement has three useful effects.

1. The bitline is shorter, so it develops its signal faster.
2. The sense amplifier and write driver for each output bit can be as wide as CM columns, which is much easier to lay out than fitting one in a single bitcell pitch.
3. Physically adjacent cells belong to different words. A particle strike that upsets several neighbouring cells therefore corrupts one bit in each of several words, which error correction can fix. Lesson 10 returns to this.

However, column multiplexing has a cost. When a wordline rises, every cell on that row turns on, including those in the columns that are not selected. Their bitlines also discharge and must be precharged again. Such cells are called half-selected. They waste energy on every read, and during a write they experience the same stress as a read – so they must have good read stability, as described in lesson 4. Higher mux factors also give longer wordlines, with more gate load and more RC delay.

5.4 Banking and segmentation

Column multiplexing alone cannot fold a very large memory into a good shape without making the wordlines too long. Large macros are therefore divided into banks (also called subarrays). Each bank has its own local row decoding and sense amplifiers. Only the bank that contains the addressed word is activated, so the others draw no dynamic power.

Related techniques split the long wires inside a bank. A divided wordline scheme uses a global wordline that selects a small group of cells through local wordline drivers, so that only the needed segment of the row turns on. A hierarchical bitline scheme connects small groups of cells to short local bitlines, which in turn connect to a global bitline. Both shorten the heavily loaded wires and reduce half-select power. The trade-off is extra periphery area and a longer control path.

Many compilers also offer each macro with its periphery in the middle – for example, the row decoder between two half-arrays – so that each wordline driver drives only half a row. This reduces wordline delay at the cost of a slightly different macro shape.

5.5 The 2048 x 64 macro at different mux factors

Figure 5.2 draws these five arrays to the same scale.

5.6 Precharge and the bitline budget

Between accesses, both bitlines of every column are returned to VDD by precharge transistors at the top of the array (Fig. 5.1). This prepares the differential read of lesson 4: a column starts at VDD on both sides, and the accessed cell pulls one side down. Because precharge must restore every column that was discharged, including half-selected ones, it consumes a significant part of the macro's dynamic power. Hence, the number of active columns per access is one of the main levers on read energy. Lesson 6 shows the precharge circuit and how its timing fits into the cycle.

5.7 Interview questions

Why do SRAMs use column multiplexing? To fold the array into a better aspect ratio, shorten the bitlines for faster reads, give each sense amplifier more than one cell pitch of width, and interleave bits of different words for soft-error protection.

What is a half-selected cell? A cell on the active wordline in a column that is not being accessed. It still discharges its bitline, wasting energy, and it sees read-like stress during a write to its row.

How is the address split for a 2048 x 64 memory with mux 8? 11 address bits in total: 8 bits select one of 256 rows and 3 bits select one of 8 columns in each group.

Why are large memories banked? To keep wordlines and bitlines short and to activate only the bank holding the requested word, which saves dynamic power and improves speed.