Lesson 1 named process simulation as half of a TCAD flow: given a proposed sequence of fabrication steps, predict the physical structure, the doping profile, the layer thicknesses, the geometry, that sequence will actually produce, before any wafer is processed. This lesson is about how that prediction is made, covering the main physical models a process simulator needs for implant, diffusion, oxidation and the etch/deposition steps this whole Manufacturing section's Lithography, Etch & CMP path covers from the process-engineering side.
Reading time: about 8 minutes.
6.1 Why simulate the process, not just the device
Lesson 4's planar MOSFET and lesson 5's FinFET and nanosheet structures were described there in terms of their finished geometry and doping. Getting to that finished structure from a bare wafer is itself the output of dozens of individual process steps, each one capable of shifting the actual result away from the idealized target: an implant that goes slightly deeper or shallower than intended, a diffusion anneal that spreads a dopant profile further than planned, an etch that undercuts a mask by a few nanometers. Process simulation models each of these steps in sequence, carrying the structure (and, critically, the three-dimensional doping profile) forward from one step to the next, so the structure handed to device simulation (lesson 7) reflects what the actual process sequence would produce, not an idealized, hand-drawn approximation of it.
6.2 Ion implantation
Ion implantation introduces dopant atoms by accelerating them to high energy and firing them into the wafer, where they come to rest at a depth and spread determined by their energy, the dopant species' mass, and the target material's stopping behavior. A process simulator models an implant's resulting profile, commonly as close to a Gaussian distribution in depth (centered at a projected range determined by implant energy, with a spread captured by a straggle parameter) for a simple case, with more detailed Monte Carlo transport models used where the simple analytic approximation is not accurate enough, for example at very shallow implants or near a mask edge where lateral spreading matters. Implant dose (total number of dopant atoms per unit area) and energy are the two parameters a process engineer most directly controls, and together they set the resulting doping concentration and depth profile the simulator predicts.
6.3 Diffusion and oxidation
After implantation, a wafer is typically annealed, heated for a controlled time and temperature, both to activate the implanted dopants (moving them onto substitutional lattice sites where they actually contribute a mobile carrier, rather than sitting in an electrically inactive interstitial position) and to repair lattice damage the high-energy implant caused. This same anneal also causes diffusion, dopant atoms spreading from their as-implanted profile, governed by a diffusion equation whose rate depends strongly on temperature and on the specific dopant species' diffusivity in silicon. A process simulator's diffusion model predicts how far and how much the as-implanted profile spreads during a given anneal's time and temperature, which matters enormously for a short-channel device: a source/drain profile that diffuses too far laterally under the gate directly worsens the short-channel effects lesson 4 described.
Oxidation, thermally growing a silicon dioxide layer by exposing the wafer to oxygen or steam at high temperature, is modeled with its own rate law (commonly a Deal-Grove-type model, capturing how growth rate depends on oxide thickness already present, since growing oxide becomes diffusion-limited as the oxide thickens and oxidant has to diffuse further to reach the silicon surface still being consumed underneath it) and matters for both gate oxide formation and the field oxide isolation structures a chip relies on.
6.4 Etch and deposition models
Process simulators also model etch and deposition, the same steps this section's Lithography, Etch & CMP path covers experimentally and conceptually: an etch model removes material following rules for a chosen etch mechanism (an idealized anisotropic etch, an isotropic etch, or a more detailed model capturing some of the aspect-ratio dependence that path's lesson 8 covered), and a deposition model adds material, with options for conformal step coverage (coating sidewalls and the bottom of a trench roughly equally) or more directional deposition, depending on which real deposition technique (covered in the Fab Equipment & Yield path) is being modeled. Because process simulation tracks three-dimensional structure through a whole sequence, a simulated etch or deposition step correctly inherits whatever topography the previous simulated steps already produced, letting an engineer see, for example, how a given etch recipe would behave on an already-non-flat surface before ever running it on a real wafer.
6.5 Worked example: simulating a source/drain extension
Assumptions: illustrative comparison only, not specific tool output. A process team is deciding between two candidate anneal conditions for a source/drain extension implant, both delivering the same implant dose and energy beforehand.
- A higher-temperature, longer anneal activates more of the implanted dose (helpful for lowering source/drain resistance) but also diffuses the profile further laterally under the gate (harmful for short-channel effects, per lesson 4.2).
- A lower-temperature, shorter anneal limits lateral diffusion, keeping short-channel behavior better, but may leave more dopant un-activated, raising source/drain resistance.
- Process simulation lets the team predict both outcomes, lateral diffusion extent and activation fraction, for several candidate anneal conditions before committing to one for the actual process flow, rather than discovering the trade-off only after fabricating and measuring real silicon for each candidate.
6.6 Interview questions
What does a process simulator predict, and why does it matter? The physical structure, including doping profile, geometry and layer thicknesses, that a proposed fabrication sequence will actually produce, letting a team evaluate process options before fabricating real silicon for each candidate.
What two parameters most directly control an ion implant's resulting profile? Implant dose (total dopant atoms per unit area) and implant energy (which sets the depth and spread via the projected range and straggle).
Why does a post-implant anneal matter for both activation and diffusion? It moves implanted dopants onto substitutional lattice sites so they contribute mobile carriers (activation), repairs implant-caused lattice damage, and simultaneously causes the dopant profile to spread (diffusion), both effects governed by the same anneal temperature and time.
What does a Deal-Grove-type oxidation model capture? How oxide growth rate depends on the oxide thickness already present, since growth becomes diffusion-limited as the oxidant must diffuse further through existing oxide to reach the silicon surface still being consumed.
Why does a longer, hotter anneal create a trade-off for a source/drain extension? It activates more of the implanted dose, lowering source/drain resistance, but also diffuses the profile further laterally under the gate, worsening short-channel effects; process simulation lets a team evaluate this trade-off computationally before committing to one anneal condition.
Key takeaways
- Process simulation predicts the physical structure, including three-dimensional doping profile, a proposed fabrication sequence will produce.
- Implant models predict a dopant's as-implanted profile from dose and energy; diffusion and activation models predict how anneal spreads and activates it.
- Oxidation models (commonly Deal-Grove-type) capture growth-rate dependence on existing oxide thickness.
- Etch and deposition models carry simulated structure forward through a sequence, inheriting whatever topography earlier steps produced.
- Process simulation lets trade-offs, like anneal temperature's activation-versus-diffusion trade-off, be evaluated computationally before real silicon is run.