Lesson 4 ended on why short-channel effects and subthreshold swing both trace back to the same root cause: the gate in a planar MOSFET only controls the channel from one side (the top), while the source and drain's own fields increasingly reach in from the sides as channel length shrinks. This lesson covers the structural answer: wrap the gate around more of the channel, so it, not the source and drain, keeps control as dimensions shrink. This is the one-sentence motivation behind the industry's move from planar to FinFET to gate-all-around.
Reading time: about 8 minutes.
5.1 Why more gate control helps
Lesson 4.2 described short-channel effects as the source and drain junctions sharing control of the channel that, ideally, only the gate should have. The more of the channel's surface area the gate physically surrounds, the harder it is for the source and drain's fields to reach into the channel's interior without the gate's own field dominating there instead. A planar MOSFET's gate controls the channel from essentially one face; a structure that wraps the gate around two, three, or all sides of a thin channel body gives the gate a correspondingly stronger grip, directly suppressing short-channel effects and DIBL, and pushing subthreshold swing closer to (though still not below, per lesson 4.4) the 60 mV/decade thermodynamic floor.
5.2 The FinFET
A FinFET turns the planar channel on its side: rather than a flat channel on the wafer surface, the channel is a thin, tall silicon "fin" standing up out of the substrate, and the gate wraps over the top and both sides of that fin (a tri-gate structure, three sides of gate control instead of a planar device's one). Current flows along the fin's length, from source to drain, through a channel now controlled from three sides rather than one.
A key practical consequence is fin quantization: a FinFET's effective channel width is set by the fin's height and thickness, which are fixed, uniform process parameters shared by every fin on the chip (etched once, to one target dimension, across the whole wafer), not an independently drawable layout parameter the way planar MOSFET width was. A circuit designer wanting a wider transistor does not draw a wider single fin; the design instead uses multiple fins in parallel, each contributing the same fixed per-fin width. Effective transistor width therefore comes in discrete steps, in units of one fin's contribution, rather than continuously: a two-fin device, a three-fin device, and so on, but nothing in between.
5.3 Nanosheet gate-all-around
Gate-all-around (GAA) pushes the same idea further: the gate surrounds the channel on all sides, not just three. A common production implementation stacks several thin horizontal silicon sheets (nanosheets) above each other, each one fully wrapped by the gate on its top, bottom, and both sides, with the gate material filling the spaces between sheets as well as around the whole stack. Current flows along each nanosheet from source to drain, with multiple sheets stacked in parallel contributing to total drive current, conceptually similar to a FinFET's multiple parallel fins, but now each individual channel has gate control on all four sides rather than three.
Nanosheet width (how wide each sheet is drawn, in the direction perpendicular to current flow) is, unlike fin quantization, a more continuously adjustable layout parameter within process-allowed limits, giving designers somewhat finer control over effective transistor width and drive strength than fin quantization's discrete per-fin steps allowed, while still retaining GAA's superior short-channel control over a FinFET.
Fabricating a nanosheet stack also requires a process step with no planar or FinFET equivalent: the sacrificial material separating the nanosheets during earlier processing (commonly a different, selectively etchable material grown in alternating layers with the final channel material) has to be removed from between the sheets before the gate is formed, so the gate can wrap each sheet fully rather than only its top and bottom. This selective removal and subsequent gate-fill step is itself a meaningful process integration challenge, tying directly back to the etch selectivity and ALD conformality concepts this section's other two paths covered, applied here to a structure neither planar nor FinFET processing ever had to solve.
| Aspect | Planar | FinFET | Gate-all-around |
|---|---|---|---|
| Gate control over channel | One side (top) | Three sides of a fin | All sides of each nanosheet |
| Effective width control | Continuous (drawn width) | Discrete (per-fin steps) | More continuous than fin quantization |
| Short-channel control | Weakest | Better than planar | Best of the three |
5.4 CFET, at a concept level
A further structural idea under active industry development is the complementary FET (CFET): stacking an n-type device directly on top of a p-type device (or vice versa), sharing the same vertical footprint rather than placing them side by side in the same horizontal plane, as every structure discussed so far in this lesson still does. The motivation is area, not short-channel control directly: a standard logic cell (an inverter, for example) needs both an n-type and a p-type device; stacking them vertically rather than laying them out side by side can meaningfully shrink the cell's footprint, continuing the industry's area-scaling roadmap even as further lateral (side-by-side) scaling of fin or nanosheet pitch becomes increasingly difficult. CFET is covered here only at this concept level, as the next structural idea beyond GAA that device and TCAD teams are actively characterizing; full PDK-level maturity and the process integration challenges of actually building two complementary devices in one vertical stack are open, active areas of development industry-wide, not a settled production reality yet at the time of writing.
5.5 Interview questions
Why does wrapping the gate around more of the channel improve short-channel effects? The more channel surface the gate physically controls, the harder it is for the source and drain's own fields to reach into the channel interior and share control that ideally only the gate should have, directly suppressing the mechanisms behind Vt roll-off and DIBL.
What is fin quantization, and what does it mean for layout? A FinFET's per-fin width is a fixed, uniform process parameter; effective transistor width is set by using multiple fins in parallel, so it comes in discrete steps (one fin's width per step) rather than as a continuously adjustable layout parameter.
How does nanosheet gate-all-around differ from a FinFET in terms of gate control? A FinFET's gate wraps three sides of the fin; a nanosheet GAA device's gate fully surrounds each stacked channel sheet on all four sides, giving stronger short-channel control.
What motivates CFET, and is it only about short-channel control? Primarily area: stacking an n-type and p-type device vertically in the same footprint, rather than side by side, shrinks a standard cell's area, continuing scaling as further lateral pitch scaling becomes harder; it is an area and density motivation more than a short-channel-control one.
Is nanosheet width a continuous or discrete layout parameter, compared to fin width? More continuous within process limits; fin width is fixed uniformly for every fin, giving only discrete per-fin steps in effective width, while nanosheet width can be drawn with finer-grained control.
Key takeaways
- More gate control over the channel directly suppresses short-channel effects and DIBL, the motivation for moving beyond planar MOSFETs.
- FinFETs wrap the gate over three sides of a vertical fin; effective width comes in discrete steps because fin dimensions are a fixed process parameter.
- Nanosheet gate-all-around surrounds stacked channel sheets on all four sides, improving short-channel control further and allowing more continuous width control than fin quantization.
- CFET stacks complementary n-type and p-type devices vertically, primarily to shrink cell area as lateral scaling becomes harder; it is an active area of industry development, not yet settled production.
- Each structural generation (planar to FinFET to GAA to CFET) trades process complexity for better gate control or density, not for a fundamentally different transport mechanism.