The Planar MOSFET

Lesson 3 built a p-n junction and a MOS capacitor separately. A planar MOSFET combines them: two p-n junctions (source and drain, both the opposite doping type from the substrate they sit in) bracketing a MOS capacitor's gate stack, with the gate's inversion layer, once formed, providing the conducting channel that connects source to drain. This lesson covers threshold voltage, the gate voltage that forms that channel, and three effects, short-channel effects, drain-induced barrier lowering, and subthreshold swing, that every later lesson in this path (FinFETs in lesson 5, compact models in lesson 9, DTCO in lesson 10) assumes as background.

Reading time: about 9 minutes.

4.1 Structure and threshold voltage

An n-channel MOSFET (NMOS) has n-type source and drain regions implanted into a p-type substrate (or a p-type well, in a technology with wells of both types), with the gate stack sitting over the region between them. Lesson 3.3 already described threshold voltage (commonly written Vt) as the gate voltage at which the MOS capacitor's inversion layer forms strongly enough to conduct. Below threshold, the channel is not inverted strongly enough, and the path from source to drain is effectively blocked by the reverse-biased source/substrate and drain/substrate junctions (lesson 3.2's reverse-bias behavior, here acting as the transistor's "off" isolation); above threshold, the inverted channel connects source and drain, and current flows, roughly proportional to how far the gate voltage exceeds Vt, for a conventional long-channel device.

4.2 Short-channel effects

The simple picture in 4.1, where the gate alone controls whether the channel conducts, holds well for a "long" channel, where L is large relative to the depletion-region widths of the source and drain junctions. As L shrinks (exactly the trend every technology node drives), the source and drain junctions' own depletion regions start to occupy a non-negligible fraction of the channel length, and a family of short-channel effects (SCE) appears, broadly: the source and drain junctions begin sharing some of the responsibility for depleting the channel that, in the long-channel picture, only the gate was doing. The most commonly cited consequence is threshold-voltage roll-off: Vt measurably decreasing as channel length shrinks, for devices on the same process, because the source and drain's own fields are doing part of what the gate alone used to have to do, so less gate voltage is needed to finish the job.

4.3 Drain-induced barrier lowering

A related, specifically drain-voltage-dependent effect is drain-induced barrier lowering (DIBL): as drain voltage increases, the drain junction's depletion region widens further into the channel, lowering the potential barrier the source has to overcome to inject carriers into the channel, even at a gate voltage that would otherwise be below threshold. The practical symptom is Vt appearing to decrease further as drain voltage increases, and, in the off state, leakage current rising with drain voltage even with the gate nominally off. DIBL is one of several leakage mechanisms a low-power design has to budget for, alongside subthreshold leakage covered next, and matters directly for why a transistor's off-state current is specified at a particular drain voltage, not as a single number independent of operating condition.

4.4 Subthreshold swing and the 60 mV/decade limit

Below threshold, a MOSFET does not switch off instantly; drain current falls off roughly exponentially as gate voltage drops further below Vt, not sharply to zero. Subthreshold swing (S) quantifies how steep that exponential fall-off is, specifically the gate voltage change needed to change drain current by one decade (a factor of 10), commonly expressed in mV/decade. A smaller S is better: it means a smaller gate-voltage swing is needed to turn the device fully off once it has turned on, which directly sets how low a supply voltage can be pushed while still keeping off-state leakage acceptably small, the central lever of low-power design covered in depth elsewhere on this site.

For a conventional MOSFET at room temperature, subthreshold swing has a hard physical floor of about 60 mV/decade. This limit comes directly from the Boltzmann distribution of carrier energies, the same underlying thermal statistics that govern how many carriers have enough energy to be thermally activated over the channel barrier at a given temperature; it is not a limitation of any particular process or device geometry, it is a consequence of using thermally distributed carriers to modulate a barrier at all, and no amount of process or geometry optimization on a conventional MOSFET can beat it. This is exactly why research beyond conventional CMOS (tunnel FETs, for example, which use quantum-mechanical tunneling instead of thermal injection over a barrier) has specifically targeted subthreshold swing below 60 mV/decade as a goal thermally-gated devices cannot reach; it is also one of the motivations, alongside better short-channel control, behind the move to FinFET and gate-all-around structures in lesson 5, which improve gate control over the channel and thereby bring S closer to that 60 mV/decade floor, without beating it outright.

4.5 Interview questions

What is threshold voltage, in terms of the MOS capacitor physics from lesson 3? The gate voltage at which the MOS capacitor's inversion layer forms strongly enough to create a conducting channel between source and drain.

What is a short-channel effect, broadly? An effect that appears as channel length shrinks, where the source and drain junctions' own depletion regions start sharing responsibility for depleting the channel that only the gate controlled in the long-channel picture; threshold-voltage roll-off (Vt decreasing as L shrinks) is the most commonly cited example.

What is DIBL, and what does it cause? Drain-induced barrier lowering: as drain voltage rises, the drain's depletion region widens into the channel, lowering the barrier to carrier injection even below threshold, causing Vt to appear to drop further and off-state leakage to rise with drain voltage.

Define subthreshold swing. The gate voltage change needed to change drain current by one decade (factor of 10) in the subthreshold region, in mV/decade; a smaller value means the device turns off more sharply.

Why is 60 mV/decade a hard limit for a conventional MOSFET at room temperature, not just a typical value? It follows directly from the Boltzmann distribution of thermally activated carrier energies; because a conventional MOSFET modulates a thermal injection barrier, no geometry or process optimization on that mechanism can beat this thermodynamic limit, which is why research into tunnel FETs and similar devices specifically targets a different physical mechanism (quantum tunneling) to get below it.