The PN Junction and MOS Capacitor

Lesson 2 ended with drift and diffusion balancing at a p-n junction with no applied bias. This lesson builds that junction up properly, then introduces the second structure every MOSFET needs: a MOS capacitor, a metal (or polysilicon) gate separated from the silicon by a thin insulator. Both structures, studied here in isolation, are the two building blocks lesson 4 assembles into a complete MOSFET.

Reading time: about 9 minutes.

3.1 The depletion region

Bring p-type and n-type silicon together at a junction (in practice, by doping adjacent regions of the same silicon crystal differently, not by physically joining two separate crystals), and the large concentration difference of each carrier type across the junction drives diffusion: holes diffuse from the p-side into the n-side, electrons diffuse from the n-side into the p-side. As each majority carrier diffuses away from its own side, it leaves behind the fixed, immobile dopant ion it was electrically neutralizing, now uncompensated: a positive ion left behind in the n-side near the junction, a negative ion left behind in the p-side. This region, stripped of mobile carriers and containing only fixed, uncompensated dopant charge, is the depletion region (or space-charge region).

The fixed charge in the depletion region sets up an electric field pointing from the n-side toward the p-side, and that field is exactly what lesson 2 described as balancing the diffusion current: it drives a drift current of the opposite sign, and at equilibrium the two exactly cancel. The potential difference across the depletion region at equilibrium is the built-in potential, set by the doping concentrations on each side and the material's intrinsic carrier concentration; for silicon at room temperature with typical doping levels, built-in potential is commonly in the range of a few tenths of a volt to around 0.7-0.9 V.

3.2 Forward and reverse bias

Applying an external voltage changes this balance. Forward bias (positive terminal to the p-side) opposes the built-in field, narrowing the depletion region and letting diffusion current dominate, current flows easily. Reverse bias (positive terminal to the n-side) adds to the built-in field, widening the depletion region and suppressing diffusion current almost entirely, current is small (ideally just a small reverse leakage current) until, at a high enough reverse voltage, breakdown mechanisms (not covered in depth in this introductory lesson) begin to dominate. This asymmetric behavior, easy conduction one way, blocked the other, is the diode behavior a p-n junction provides, and is also the physical basis of the source/drain junctions that bound every MOSFET, covered next in lesson 4.

3.3 The MOS capacitor

A MOS (metal-oxide-semiconductor) capacitor is, structurally, just a conductive gate separated from a doped silicon substrate by a thin insulating oxide: no source, no drain, nothing a circuit would directly use on its own, but it is the exact structure a MOSFET's gate stack is built from, and understanding its behavior in isolation makes the MOSFET in lesson 4 much easier to follow. Consider a MOS capacitor built on p-type substrate, and sweep the gate voltage from negative to positive:

• Accumulation (gate voltage sufficiently negative): the negative gate voltage attracts the substrate's majority carriers, holes, toward the oxide interface, accumulating an excess of holes right at the surface.
• Depletion (gate voltage moderately positive): the positive gate voltage repels holes away from the interface, exposing the fixed negative acceptor ions beneath them, exactly analogous to the p-n junction's depletion region in 3.1, except here the "other side" is the gate itself across the oxide, not another doped silicon region.
• Inversion (gate voltage sufficiently positive): past a threshold, the positive gate voltage is strong enough to attract minority carriers, electrons, to the interface in large enough numbers that a thin layer at the very surface now behaves like n-type silicon, inverted from the p-type substrate beneath it. This inversion layer is precisely the conducting channel a MOSFET relies on, which is exactly why lesson 4 opens with threshold voltage, the gate voltage at which this inversion layer forms strongly enough to conduct.

3.4 The C-V curve

Each of these three regimes has a distinctly different capacitance between gate and substrate, measurable experimentally by sweeping gate voltage and measuring capacitance (a C-V, capacitance-voltage, measurement), one of the most common and informative characterization techniques in device engineering. In accumulation, capacitance is high and roughly constant, set by the oxide thickness alone (the hole accumulation layer acts almost like the second capacitor plate right at the oxide surface). Moving into depletion, capacitance drops as the depletion region widens, adding its own depletion capacitance in series with the oxide capacitance, lowering the total. Deep into inversion, capacitance rises again (at low measurement frequency; at high frequency, a subtlety beyond this lesson's scope, the inversion layer cannot respond fast enough and the curve instead flattens near its depletion-region minimum). The characteristic dip shape of a C-V curve is, in practice, one of the first things a device engineer looks at to check oxide thickness, doping concentration, and threshold voltage are all tracking where they should be, before even running a full transistor measurement.

3.5 Interview questions

What is the depletion region, physically? The region near a p-n junction stripped of mobile carriers, containing only fixed, uncompensated dopant ions left behind as majority carriers diffuse away from the junction, with an electric field set up by that fixed charge.

What sets the built-in potential of a p-n junction? The doping concentrations on each side and the material's intrinsic carrier concentration; it is the equilibrium potential difference across the depletion region with no external bias applied.

Name the three regimes of a MOS capacitor as gate voltage sweeps from negative to positive on a p-type substrate. Accumulation (majority carriers, holes, pulled to the interface), depletion (holes repelled, exposing fixed acceptor ions), and inversion (minority carriers, electrons, pulled to the interface in large enough numbers to form a conducting channel).

Why does a MOS capacitor's inversion layer matter for a MOSFET? It is the same thin, inverted conducting layer that becomes a MOSFET's channel; the gate voltage needed to form it strongly enough to conduct is the transistor's threshold voltage.

What does a C-V curve's characteristic dip shape tell a device engineer? It is a quick check that oxide thickness, substrate doping and threshold voltage are tracking expected values, since each regime's capacitance (set by oxide capacitance alone in accumulation, lowered by series depletion capacitance in depletion, and rising again in inversion at low frequency) depends on those parameters.