Foundations path

RTL & Logic Design

A free 12-lesson path from specification to synthesizable RTL: Boolean minimization, combinational blocks, programmable logic, state machine design and encoding, counters, hazards, and arithmetic datapaths from adders to floating point, every example verified in simulation.

12
lessons
Beginner to Intermediate
level
Free
every lesson
Start with lesson 1 →

RTL & Logic Design

  1. 1What RTL and Logic Design IsAbstraction levels in Verilog, what RTL actually means (datapath plus control), and the spec-to-silicon design loop every lesson in this path follows.
  2. 2From Boolean Algebra to LogicThe Boolean laws used in practice, SOP and POS forms, don't-cares, and static hazards in combinational logic, with a verified minimized Verilog implementation.
  3. 3Combinational Building BlocksParameterized mux trees, decoders, priority encoders, and comparators in Verilog, with a note on how each one synthesizes.
  4. 4Programmable Logic and Lookup TablesPROM, PAL, and PLA architecture at a conceptual level, how it leads to the FPGA LUT, and a verified case-statement ROM in synthesizable Verilog.
  5. 5Synchronous State Machine DesignThe FSM design method: spec to state diagram, state table, encoding, equations and RTL, with a 1101 detector built as Moore and Mealy and verified.
  6. 6State Minimization and EncodingFinding and merging equivalent states by row-matching, then comparing binary against one-hot state encoding with real synthesized gate and flip-flop counts.
  7. 7Registers, Shift Registers, and CountersEnabled registers, modulo-N up/down counters, Johnson and ring counters, and a maximal-length LFSR, each built in Verilog and verified in simulation.
  8. 8Asynchronous Logic, Hazards, and RacesHow hazards, critical races and oscillation arise in asynchronous logic, and why RTL design stays synchronous and crosses clock domains with synchronizers.
  9. 9Adders and Carry Logic in RTLTurn the half/full adder and carry-lookahead equations into verified Verilog: ripple-carry, carry-lookahead and carry-select adders, compared by critical path.
  10. 10Subtraction, Multiplication and Division in RTLTwo's-complement subtraction with overflow detection, Booth recoding for multiplication, and a restoring-division datapath built and verified in Verilog.
  11. 11ALUs and Decimal Arithmetic in RTLDesign a small ALU from an opcode table with zero/carry/overflow/negative flags, then build BCD addition with +6 correction and 9's-complement BCD subtraction.
  12. 12Floating Point and a Datapath ProjectThe floating-point add algorithm (align, add, normalize, round) worked by hand, then a capstone datapath and FSM controller taken from spec to verified RTL.