ICC2: Design import Cheat Sheet

This stage covers bringing the design into ICC2: loading the netlist and reference libraries, reading a supplied floorplan DEF, connecting power and ground, and confirming power domains against the design inventory.

Sanity check cheat sheet

One row per command card. Read left to right: the check, the command that answers it, then what a healthy result, a result to review and a hard stop look like.

Card	Check and when	Command	Healthy	Review	Hard stop
I-01	Load the design Import	`create_lib <lib> -ref_libs {<ref_a> <ref_b>}` `read_verilog <design.v>` `current_block`	No errors. Warnings are known for this library set. The top module is the one expected.	New warning IDs, for example about unresolved references that are later bound.	Any error, a module that cannot be resolved, or a top module different from the specification.
I-02	Reference library binding After import	`report_ref_libs` `link_block -rebind`	Each reference library is open and bound as intended.	A library found through a path that the methodology did not list.	A cell with no reference library, or a block bound to the wrong library.
I-03	Netlist and library consistency After import	`check_design` †	Only the intended exceptions appear, each on the written list.	Physical-only cells such as fillers; compare with the library.	A functional cell with no timing model, no physical view, or an undriven input on a functional path.
I-04	Design inventory against synthesis After import	`report_cells` `get_cells -hier <pattern>`	Counts match the synthesis report, or differ by a known amount.	A small unexplained difference.	A large difference in instances or ports, usually a wrong netlist file or top module.
I-05	Floorplan data read from DEF When a DEF is supplied	`read_def -syntax_only <block.def>` `check_duplicates -remove`	Syntax check is clean, and no duplicate shapes or vias remain after the read.	Site name or object mismatches that the read ignored.	Syntax errors, or duplicate shapes left in the block.
I-06	Power and ground connection After import	`connect_pg_net -automatic` `check_mv_design -pg_pin`	No PG pin is left unconnected in the check output.	Pins on physical-only cells that are tied later by design.	A PG pin of a functional cell or macro left unconnected or on a signal net.
I-07	Power domains After import and UPF load	`report_power_domains` `report_mv_design`	Domains match the power intent, and the default domain is replaced where UPF is loaded.	Extra domains with a recorded reason.	A domain missing from the report, or a cell in a domain the intent does not allow.

Command cheat sheet

ICC2 commands. Angle brackets are placeholders, and values shown are examples, not project limits. A dagger (†) marks a command the notes behind this book do not fully cover; it is shown without options, so confirm it with man or help in your release.

Create library and read design
`create_lib <lib> -ref_libs {<ref_a> <ref_b>}`	A design library with reference libraries attached. Changes the session; record it.
`read_verilog <design.v>`	The netlist read into a block. The top module is detected as the one no other module instantiates.
`current_block`	The block that holds the imported design.
`open_block <block>`	Opens an existing block, for a restart from a saved stage.
Linking and reference libraries
`report_ref_libs`	The reference libraries of the open library with open and technology markers.
`set_ref_libs -add <blk.ndm>`	Adds a reference library, for example a lower-level block. Changes the session; record it.
`link_block -rebind`	Rebinds blocks already in the library to current reference libraries. Changes the session; record it.
Floorplan input from DEF
`read_def <block.def>`	Annotates floorplan data onto the current block. Existing floorplan information is kept by default.
`read_def -syntax_only <block.def>`	A syntax check of the DEF, with no change to the block.
`read_def -no_incremental <block.def>`	Removes existing floorplan information first, so the placement area comes only from DEF site rows. Changes the session; record it.
`read_def -convert_sites {{<def_site> <lib_site>}} <block.def>`	Maps site names that differ between the DEF and the library.
`read_def -add_def_only_objects {cells\|nets\|ports\|all} <block.def>`	Creates objects that exist only in the DEF. Without it these objects are ignored.
`check_duplicates -remove`	Removes duplicate shapes and vias after a DEF read.
`set_app_options -name file.def.rule_based_name_matching -value false`	Turns off rule-based name matching for DEF names. Changes the session; record it.
Inventory
`report_cells`	The cells of the block, for comparison with the synthesis report.
`get_cells -hier <pattern>`	A collection of cells at any hierarchy level that match the pattern.
`get_lib_cells <lib>/<pattern>`	The library cells that match the pattern.
`report_lib`	The loaded library content, to confirm the intended libraries are present.
Power and ground connection
`connect_pg_net -automatic`	Connects PG pins using the power intent. Changes the session; record it.
`connect_pg_net -net <net> [get_pins */<pin>]`	A manual PG connection for the named pins. Changes the session; record it.
Power intent and checks
`report_power_domains`	The power domains of the block.
`report_mv_design`	A summary of multivoltage information.
`check_mv_design`	Electrical and power-intent violations. Add -pg_pin for PG pin connectivity or -isolation for isolation.
`check_design` †	Design checks on netlist and library consistency.