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Innovus + ICC2 Qualification Cheat Sheets

Commands and what they produce, for all sixteen qualification stages, in both Cadence Innovus (Legacy UI) and Synopsys ICC2. Free to read online; both PDFs are a paid download.

32
stages
Intermediate
level
Free
every stage
Get Innovus + ICC2 Cheat Sheets at ₹199

Cadence Innovus (Legacy UI)

  1. 1Tool, project and session qualificationCovers verifying the Innovus release and build, UI mode, log and message history, non-default settings, compute resources, and checkpoint provenance at session start.
  2. 2Design import and database sanityCovers netlist and library load, library binding and black boxes, netlist structure and uniqueness, design inventory, technology layers, and power and ground identity after import.
  3. 3SDC, MMMC and timing-environment qualificationCovers active view coverage, clock definitions, constraint consistency, case analysis and exceptions, analysis mode, timing-check coverage, and baseline timing rules.
  4. 4Floorplan, macro and pin qualificationCovers die and core geometry, floorplan legality and utilisation, macro placement and overlap, pin assignment, early routability, and a PG connectivity snapshot.
  5. 5Power-planning qualificationCovers PG and tie-pin connection, physical-only cells, rings and stripes, followpins, power vias, special-net connectivity against baseline, grid DRC, and track budget.
  6. 6Pre-placement readinessCovers fixed and preplaced baselines, dont_use and dont_touch restrictions, blockages and padding, tie cells, scan chains, placement settings, timing readiness, and congestion risk before placement.
  7. 7Placement and post-placement qualificationCovers the placement run log, placement legality, fixed and dont_touch preservation, density and congestion, physical and tie connections, post-placement timing, DRVs, and pre-CTS optimisation.
  8. 8Clock tree synthesis readinessCovers clock definitions and propagation state, constants and gating, clock net routing rules, cell lists, skew targets, clock tree specification, sinks, insertion delays, halos, and the CTS prerequisite gate.
  9. 9CTS and post-CTS qualificationSanity checks and commands for clock tree synthesis setup, skew groups, clock DRVs, post-CTS timing, hold fixing, and clock gating coverage.
  10. 10Global and early routing qualificationSanity checks and commands for the routing set-up record, early global route congestion, hotspots, layer usage, route guides, and congestion relief.
  11. 11Detailed-route qualificationSanity checks and commands for detailed routing readiness, DRC and antenna verification, via counts, special-net integrity, and post-route timing status.
  12. 12Post-route optimisation qualificationSanity checks and commands for post-route setup and hold optimisation, DRC and SI results, physical integrity, and area and power recovery.
  13. 13Chip finishing and post-fill qualificationSanity checks and commands for filler and tap/end-cap insertion, metal and via fill, density verification, post-fill DRC, and stream-out readiness.
  14. 14Extraction and signoff correlationSanity checks and commands for RC corner and extraction mode records, parasitic annotation, SPEF comparison, scale factors, and in-tool versus signoff timing.
  15. 15ECO and incremental requalificationSanity checks and commands for baseline checkpoints, ECO mode settings, netlist-driven and interactive edits, ECO place and route, and post-ECO requalification.
  16. 16Final implementation handoffSanity checks and commands for the final freeze: run identity, physical closure, timing on the frozen database, and netlist, DEF, stream and parasitic export for hand-off.

Synopsys IC Compiler II (ICC2)

  1. 1Tool, project and sessionSanity checks and commands for release versions, library and block scope, reference libraries, search paths, licences and session saves.
  2. 2Design importSanity checks and commands for reading the netlist and DEF, binding reference libraries, and connecting power and ground after import.
  3. 3SDC, MMMC and timing environmentSanity checks and commands for modes, corners, scenarios, SDC reads, clock definitions, constraint completeness and baseline timing.
  4. 4Floorplan, macro and pinsSanity checks and commands for die and core geometry, floorplan legality, macro and pin placement, and voltage area setup.
  5. 5Power planningSanity checks and commands for PG connections, tap and boundary cells, PG mesh construction, missing vias, rail analysis and routability.
  6. 6Pre-placement readinessSanity checks and commands for legality, dont-touch scope, blockages, tie cells, scan data and congestion before placement starts.
  7. 7Placement and post-placementSanity checks and commands for the place_opt run, legality, protected objects, congestion, tie and scan, and post-placement timing quality.
  8. 8CTS readinessSanity checks and commands for clock definitions, ideal state, clock routing rules, cell purpose lists and balancing before clock tree synthesis.
  9. 99. CTS and post-CTSSanity checks and ICC2 commands for clock tree prerequisites, running clock_opt, QoR, skew, balance groups, routes, and clock power.
  10. 1010. Global and early routingSanity checks and ICC2 commands for layer constraints, routability, global route runs, congestion review, and wire length statistics.
  11. 1111. Detailed routeSanity checks and ICC2 commands for route_auto, DRC and antenna checks, LVS connectivity, repairing violations, redundant vias, and signoff DRC.
  12. 1212. Post-route optimisationSanity checks and ICC2 commands for scenario setup, baseline timing, route_opt runs, CCD, hold, routing integrity, signoff DRC and clock power.
  13. 1313. Chip finishing and post-fillSanity checks and ICC2 commands for filler, boundary and tap cells, metal fill, isolated vias, signoff DRC and routing, antenna and LVS checks.
  14. 1414. Extraction and signoff correlationSanity checks and ICC2 commands for parasitic extraction settings, routing readiness, timing update, parasitic hand-off, and rail analysis.
  15. 1515. ECO and incremental requalificationSanity checks and ICC2 commands for ECO baselines, freeze-silicon mode, spare cells, netlist-driven edits, placement, routing and timing impact.
  16. 1616. Final handoffSanity checks and ICC2 commands for run identity, physical closure, save and restore, netlist, DEF, stream and constraint files for tape-out hand-off.