Innovus: Design import and database sanity Cheat Sheet

This stage checks that the design came in correctly: the netlist, LEF and MMMC files loaded as intended, the library binding has no accidental black boxes, the netlist structure is sound, the design inventory matches synthesis, the technology layers are present, and power and ground identity is correct.

Sanity check cheat sheet

One row per command card. Read left to right: the check, the command that answers it, then what a healthy result, a result to review and a hard stop look like.

Card	Check and when	Command	Healthy	Review	Hard stop
I-01	Load the design Import	`set init_verilog <netlist.v>` `set init_lef_file {<tech.lef> <cells.lef> <macros.lef>}` `set init_mmmc_file <views.tcl>` `set init_top_cell <top>` `set init_pwr_net VDD` `set init_gnd_net VSS` `init_design`	No errors. Warnings are known for this library set.	New warning IDs, for example about sites or pins in a cell LEF.	Any error, or a warning that a cell has no library model or a module could not be resolved.
I-02	Library binding and black boxes After import	`check_design -type "library netlist" -out_file <f>` `checkDesign -netlist -physicalLibrary -timingLibrary -powerGround \ -noHtml -outfile <f>`	Only the intended exceptions appear, each on the written list.	Physical-only cells that are known fillers or other physical-only cells; review them against the library.	A functional cell with no timing model, a cell with no LEF, a multiply driven net, or an undriven input on a functional path.
I-03	Netlist structure and uniqueness After import	`checkNetlist -outfile <f>` `checkUnique -verbose`	checkNetlist rule section clean; checkUnique returns 1.	Rule findings on test or spare logic that the methodology accepts.	checkUnique returns 0 before optimisation in a flat flow.
I-04	Design inventory against synthesis After import	`reportNetStat` `reportGateCount -stdCellOnly -outfile <f>` `report_area -detail -out_file <f>`	Every count matches the synthesis report, or differs by a known amount such as physical-only cells added by a script.	A small unexplained difference.	A large difference in instances or ports, which usually means a wrong netlist file or a different top cell.
I-05	Technology layers and preplaced objects After import	`dbGet head.layers.extName` `dbGet -p top.insts.pStatus fixed` `dbGet top.insts.?`	Routing layers match the technology LEF; FIXED count is zero, or equals the macros fixed by an imported floorplan.	Extra layers that the methodology does not route on.	Missing layers, or FIXED instances nobody expected.
I-06	Power and ground identity After import	`globalNetConnect VDD -type pgpin -pin VDD -all` `checkDesign -netlist -physicalLibrary -timingLibrary -powerGround \ -noHtml -outfile <f>`	No PG pin left unconnected in the checkDesign report.	Pins on physical-only cells that are tied later in the flow by design.	A PG pin of a functional cell or macro left unconnected, swapped between power and ground or on a signal net.

Command cheat sheet

Legacy UI commands. Angle brackets are placeholders, and values shown are examples, not project limits.

Load the design
`set init_verilog <netlist.v>`	The gate-level netlist file that init_design will read.
`set init_lef_file {<tech.lef> <cells.lef>}`	The LEF list, technology LEF first.
`set init_mmmc_file <views.tcl>`	The MMMC view file that defines library sets, corners and views.
`set init_top_cell <top>`	The top cell to build the database for.
`set init_pwr_net VDD`	The power net name for the design.
`set init_gnd_net VSS`	The ground net name for the design.
`init_design`	The design database built from the init_* globals. Works only when no design or library is loaded yet.
`set init_design_uniquify 1`	Uniquifies the design during the read and flatten. Default 0. Optimisation is not allowed on a non-unique design.
`set init_verilog_tolerate_port_mismatch 0`	Default. The netlist read stops with an error when instance ports do not match the cell. Keep it at 0 for qualification.
`set init_lef_check_antenna 1`	Default. Warnings for LEF pins with zero antenna gate or diff area.
`getImportMode -treatUndefinedCellAsBbox`	Whether undefined cells are read as black boxes. Default false. The provided reference documents the read form only.
Library and netlist checks
`check_design -type library -out_file <f>`	Cells with LEF but no .lib (physical-only) and with .lib but no LEF (logical-only).
`check_design -type netlist -out_file <f>`	Undriven, multiply driven and unloaded nets, constant-driven pins, feedthrough modules and empty modules.
`check_design -type "library netlist" -out_file <f>`	Both of the above in one table, with the full detail in the out file. Stops the script if errors are found.
`check_design -type assign_statements -out_file <f>`	Assign statements in the netlist, checked before writing a netlist out.
`checkDesign -netlist -noHtml -outfile <f>`	Output pins tied to power or ground, floating inputs and multiple-driver nets, as a text report. Add -danglingNet to list nets with no instance or top-level terminal.
`checkDesign -physicalLibrary -noHtml -outfile <f>`	Cells not defined in LEF, plus LEF cells with missing dimensions, pin direction or geometry, sizes that are not a site multiple, or macros without full obstruction.
`checkDesign -timingLibrary -noHtml -outfile <f>`	Cells used in the design that are not defined in the timing library.
`checkDesign -powerGround -noHtml -outfile <f>`	Power and ground pins that are unconnected or connected to the wrong net.
`checkDesign -tieHiLo -noHtml -outfile <f>`	Unconnected tie-high and tie-low terminals, and tie pins on different P/G nets.
`checkDesign -io -noHtml -outfile <f>`	Unplaced I/O cells and pins, floating I/O pad pins, I/O pins tied to core cells.
`checkDesign -all -noHtml -outfile <f>`	All checkDesign categories in one text report.
`checkNetlist -outfile <f>`	Design summary, design statistics, I/O pad summary and design rule checks.
`checkNetlist -outfile <f> -includeSubModule`	The same report plus port-definition checks for submodules.
`checkUnique`	Returns 1 if every non-leaf module is instantiated once, 0 if not.
`checkUnique -verbose`	The same result with the detail of what is not unique.
`checkTimingLibrary -outfile <f>`	Inconsistencies in the loaded timing libraries.
`checkTimingLibrary -checkPower -outfile <f>`	The same, plus cells without power constructs such as leakage or internal power.
`reportDanglingPort -outfile <f>`	Ports disconnected inside and outside a module, or connected inside but not outside.
`reportDanglingNet -outfile <f>`	The total net count and the number of dangling nets with zero terminals, including PG nets, and how many are removable.
Inventory
`reportNetStat`	Counts of cells, nets, pins and I/Os, nets by number of terminals, and the primitives used.
`reportGateCount -outfile <f>`	The design size in gate counts, using the dbgSitesPerGate gate size (default 3).
`reportGateCount -stdCellOnly -outfile <f>`	Gate count from standard-cell area only, excluding blocks and I/O cells.
`reportGateCount -level 1 -outfile <f>`	Gate counts for the top module and one level of children. Modules of 1000 gates or fewer are ignored unless -limit is given.
`report_area -summary`	The area summary for the whole design.
`report_area -detail -out_file <f>`	Area per module plus a breakdown by cell type.
`report_area -include_physical -out_file <f>`	Area including physical-only cells, which are excluded by default.
`report_gates -out_file <f>`	The library cells used and their source libraries, cell area, and the split into timing models, sequentials, clock gates, inverters, buffers and logic.
`report_sequential -out_file <f>`	The sequential elements of the design: flops, latches and clock gates.
`report_preserves`	Every preserve that affects optimisation: dont_touch, read_only, dont_use and use_cells attributes with non-default values.
`report_preserves -dont_use`	Only the dont_use and use_cells settings.
Database queries
`dbGet top.numInsts`	The number of instances in the top cell.
`dbGet top.terms.name`	The names of all top-level ports, one per bit. Count them with llength.
`dbGet top.nets.name`	The names of all nets in the top cell.
`dbGet -u top.insts.cell.name`	The unique list of library cells used in the design.
`dbGet head.libCells.name`	The names of all loaded library cells.
`dbGet head.layers.extName`	All technology layers in stack order: routing layers, cut layers and OVERLAP.
`dbGet -p top.insts.pStatus fixed`	Pointers to every instance whose placement status is fixed. An empty result prints 0x0, so add -e before taking llength.
`dbGet top.insts.isDontTouch 1 -p`	Pointers to every dont_touch instance.
`dbGet top.insts.?`	The attribute names available on instances. Use it before scripting an attribute.
`getDbGetMode`	The current setDbGetMode settings, such as the display limit for long lists.
`report_metal_stack`	Each routing layer with its preferred direction, track offset and pitch, minimum width and spacing, and default wire width.
PG ties
`globalNetConnect VDD -type pgpin -pin VDD -all`	Logical connection of every PG pin named VDD to net VDD. Pin names are library-specific.
`globalNetConnect VSS -type pgpin -pin VSS -all`	The same for ground.
`globalNetConnect VDD -type tiehi -all`	Connects pins tied to constant 1'b1 to net VDD.
`globalNetConnect VSS -type tielo -all`	Connects pins tied to constant 1'b0 to net VSS.