This stage checks the power grid after it is built: PG and tie-pin connection, physical-only cell coverage, ring and stripe geometry, followpins and macro pin connection, power via coverage, special-net connectivity against the Chapter 4 baseline, grid design-rule compliance, and the routing track budget the grid leaves behind. It also covers rework commands for rebuilding the grid and optional UPF power-domain checks.
Sanity check cheat sheet
One row per command card. Read left to right: the check, the command that answers it, then what a healthy result, a result to review and a hard stop look like.
| Card | Check and when | Command | Healthy | Review | Hard stop |
|---|---|---|---|---|---|
| P-01 | PG and tie-pin connection After global net connection |
checkDesign -powerGround -noHtml -outfile <f>checkDesign -tieHiLo -noHtml -outfile <f>globalNetConnect <pg_net> -type pgpin -pin <pg_pin> -all -verbose |
Every rule connects the count you expect, and the check reports no PG findings and no unconnected tie terminals. | A rule that connects zero pins, which usually means a misspelled pin name, or a tie terminal on a net that differs from its PG pin. | Any terminal on the wrong supply net, or floating PG terminals on standard cells or macros. |
| P-02 | Physical-only cells After the floorplan, before rings |
addEndCap -prefix <prefix>addWellTap -cell <tap_cell> -cellInterval <um> -prefix <prefix>getEndCapMode |
End caps at every row end, and taps at the intervals the rule requires. | Rows that the well-tap check does not cover. The reference states it does not check row areas covered by blocks and their halos or by placement blockages. | Missing end caps or missing taps where the rule applies. |
| P-03 | Rings and stripes After connection rules |
getAddRingModesetAddRingMode -stacked_via_bottom_layer <layer> -stacked_via_top_layer <layer>addRing -nets {<pwr_net> <gnd_net>} -type core_rings -follow core \ |
Geometry equals the specification, the ring is closed with vias at its corners, and stripe sets cover the whole core. | Default stacked-via limits that cut through unwanted layers, or a set-to-set distance that leaves a wide strip of core with no stripe, often beside macros. | A ring side missing, a stripe pair with the nets reversed, a layer the specification does not allow, or a short between the two nets. |
| P-04 | Followpins and macro pin connection After stripes |
getSrouteModesroute -connect corePin -nets {<pwr_net> <gnd_net>} -corePinTarget firstAfterRowEnd \sroute -connect blockPin -nets {<pwr_net> <gnd_net>} -blockPin useLef \ |
Every row and every macro PG pin has a connection to the grid, and the placement check lists no missing followpin or rail-alignment entry. | Connections that exist but land on a different layer from the plan. | A row with no followpin, or a macro PG pin with no connection. |
| P-05 | Power vias After followpins |
verifyPowerVia -net {<pwr_net> <gnd_net>} -report <f>verifyPowerVia -net {<pwr_net> <gnd_net>} -stackedVia -layerRange {<bottom_layer> <top_layer>} \editPowerVia -add_vias 1 -nets {<pwr_net> <gnd_net>} -bottom_layer <layer> -top_layer <layer> |
No missing vias, and the multi-cut share matches the plan. | A high single-cut share on a layer pair that the plan expected to be multi-cut. | A missing via at a crossing of same-net wires, or a stacked via that is incomplete. |
| P-06 | Special-net connectivity against the baseline After vias |
verifyConnectivity -net {<pwr_net> <gnd_net>} -type special -noAntenna -report <f>verifyConnectivity -net {<pwr_net> <gnd_net>} -type special -noAntenna -allPGPinPort \ |
Opens fall from the baseline to none, with the same command form in both runs. | Unconnected pins on cells that are intentionally not powered, which must be listed and explained. | Any open on a supply net, or any unconnected macro PG port. |
| P-07 | PG shorts and grid design rules After connectivity is clean |
verify_drc -check_only special -limit 0 -report <f>verify_drc -check_only special -check_short_only -report <f>get_verify_drc_mode |
No violations, and the report was produced by the same stored settings you record. | An empty report from a run that completed, which proves only that the checker ran. | Any short between VDD and VSS, or between a supply wire and a signal net. |
| P-08 | Track budget and routing resource left After the grid is final |
report_metal_stackreport_tracks -prefer_onlyreport_route -track_utilization -layer <bottom_layer>:<top_layer> |
The routing resource left on each layer meets the project budget. | One layer carrying far more PG than its neighbours, which pushes routing to other layers. | Free tracks on a layer below the project budget, because the router has nothing to work with. |
Command cheat sheet
Legacy UI commands. Angle brackets are placeholders, and values shown are examples, not project limits.
| Global net connection and tie pins | |
|---|---|
checkDesign -powerGround -noHtml -outfile <f> | Text report of power terminals on ground nets, ground terminals on power nets, floating PG terminals and PG terminals on other nets. Writes a file. |
checkDesign -tieHiLo -noHtml -outfile <f> | Text report of unconnected tie-high and tie-low terminals, and of tie pins and PG pins connected to different nets. Writes a file. |
getTieHiLoMode -nonDefault | The setTieHiLoMode settings that are not at their default value. |
writeFPlanScript -fileName <f> -sections {globalNetConnect} | The global net connections written as Tcl commands you can review and source later. Writes a file. |
globalNetConnect <pg_net> -type pgpin -pin <pg_pin> -all -verbose | Connects the named PG pin of every instance to the global net and prints statistics. Changes the database. |
globalNetConnect <pg_net> -type pgpin -pin <pg_pin> -singleInstance <inst> -override | Connects one instance, typically a macro with its own pin names, and replaces earlier connections. Changes the database. |
globalNetConnect <pg_net> -type net -hierInst <hinst> -net <net_basename> | Moves the connections of a named net under a hierarchical instance onto the global net. Changes the database. |
globalNetConnect <power_net> -type tiehi | Connects tie-high pins directly to the power net. addTieHiLo overrides this later. Changes the database. |
globalNetConnect <ground_net> -type tielo | Connects tie-low pins directly to the ground net. Changes the database. |
clearGlobalNets | Removes every logical PG and tie connection. Changes the database; use it only before rebuilding the rules. |
| Physical-only cells | |
verifyEndCap -report <f> | Markers and a report for missing end-cap cells and end caps of the wrong type. |
verifyEndCap -wrongLocation -report <f> | Adds a check that end caps sit in the right location. |
verifyWellTap -report <f> | Markers and a report for missing well taps and taps that break the distance rule, with the actual and rule distance. It does not check row areas covered by blocks and their halos or by placement blockages. |
verifyWellTap -cell <tap_cell> -rule <um> -report <f> | The same check with the tap cell and distance taken from the project rule. |
getEndCapMode | The stored setEndCapMode settings. |
get_well_tap_mode | The stored set_well_tap_mode settings. |
addEndCap -prefix <prefix> | End-cap cells at the row ends, with preplaced status. Changes the database. |
addWellTap -cell <tap_cell> -cellInterval <um> -prefix <prefix> | Well-tap cells at the given maximum interval, with preplaced status. Changes the database. |
deleteFiller -prefix <prefix> | Removes physical cells that carry the prefix. The default prefix is FILLER, so pass the end-cap or tap prefix you used. Changes the database. |
| Mode settings to record | |
getAddRingMode | The stored values of every setAddRingMode option. |
getAddStripeMode | The stored values of every setAddStripeMode option. |
getSrouteMode | The stored values of every setSrouteMode option. |
getViaGenMode | The stored values of every setViaGenMode option, which also steer the power vias. |
| Rings, stripes and followpins | |
setAddRingMode -stacked_via_bottom_layer <layer> -stacked_via_top_layer <layer> | Limits the layers that ring vias can stack through. Changes the session settings. |
addRing -nets {<pwr_net> <gnd_net>} -type core_rings -follow core -layer {top <h_layer> bottom <h_layer> left <v_layer> right <v_layer>} -width <w> -spacing <s> -offset <o> | Core rings around the core boundary. Changes the database. |
setAddStripeMode -stacked_via_bottom_layer <layer> -stacked_via_top_layer <layer> | Limits the layers that stripe vias can stack through. Changes the session settings. |
addStripe -nets {<pwr_net> <gnd_net>} -layer <layer> -direction vertical -width <w> -spacing <s> -set_to_set_distance <d> -start_offset <o> | A set of stripes on one layer. Changes the database. |
addStripe -report_cut_stripe <f> | Writes a DRC marker file for stripes that were cut to avoid a violation. Run it as part of an addStripe call. |
sroute -connect corePin -nets {<pwr_net> <gnd_net>} -corePinTarget firstAfterRowEnd -allowLayerChange 1 -layerChangeRange {<bottom_layer> <top_layer>} | Followpin wires from the standard-cell PG pins to the grid. Changes the database. |
sroute -connect blockPin -nets {<pwr_net> <gnd_net>} -blockPin useLef -blockPinTarget nearestTarget -inst {<macro_inst>} | Wires from macro PG pins to the nearest legal target. Changes the database. |
setViaGenMode -viarule_preference {<rule1> <rule2>} -optimize_cross_via 1 | Sets the preferred via rules and minimum-enclosure crossover vias before the power commands. Changes the session settings. |
| Power vias | |
verifyPowerVia -net {<pwr_net> <gnd_net>} -report <f> | Markers and a report of missing vias where orthogonal power wires on adjacent layers cross. |
verifyPowerVia -net {<pwr_net> <gnd_net>} -stackedVia -layerRange {<bottom_layer> <top_layer>} -report <f> | Adds the check for missing stacked vias between the bottom and top layers, plus the adjacent vias between them. The reference does not state the combined effect with -stackedVia. |
report_via -special | Single-cut and multi-cut summary of the special vias. |
reportPowerRoute -followpin_cut_ratio {<cutclass1> <w1> <cutclass2> <w2>} -net <net> | Cut ratio of followpin via stapling. Needs two cut classes defined in the LEF. |
editPowerVia -add_vias 1 -nets {<pwr_net> <gnd_net>} -bottom_layer <layer> -top_layer <layer> | Adds power vias between the layers. Changes the database. |
editPowerVia -add_vias 1 -nets {<pwr_net> <gnd_net>} -cell_pins {<macro_cell>:<pg_pin>} | Drops vias on the named macro PG pins. Changes the database. |
| Connectivity and geometry | |
verifyConnectivity -net {<pwr_net> <gnd_net>} -type special -noAntenna -report <f> | Opens and unconnected PG pins on the named nets, with markers. The same form as the Chapter 4 baseline. |
verifyConnectivity -net {<pwr_net> <gnd_net>} -type special -noAntenna -allPGPinPort -report <f> | Adds a check of all PG ports, for macros with several ports per pin. |
verify_drc -check_only special -limit 0 -report <f> | Markers and a report of violations between special routes and other shapes, without the default cap of 1000. |
verify_drc -check_only special -check_short_only -report <f> | Only the shorts involving special routes. |
get_verify_drc_mode | The current verify_drc settings. |
violationBrowser -connectivity | Opens the browser on connectivity markers only. |
saveDrc <f> | Writes DRC markers to a file without saving the whole design. The reference documents it for verify_drc and verifyMetalDensity markers, so connectivity markers are not verified. Writes a file. |
| Track budget | |
report_metal_stack | Direction, offset, pitch, minimum spacing, minimum width and default wire width of every routing layer. Uniform track patterns only, and the preferred direction by default. |
report_tracks -prefer_only | The track definitions of each layer in its preferred direction. |
report_route -track_utilization -layer <bottom_layer>:<top_layer> | Per layer: tracks, share blocked by the PG mesh, blockages, cells and nets, and the share still available. |
report_pg_keepout | Every PG keepout box in the design. |
| Rework and checkpoint | |
defOutBySection <f> -specialNets -specialNetRouting | The special nets with their routing written to a DEF file, which is the way to keep the grid outside the database. It also writes the die area, components and nets unless suppressed. Writes a file. |
saveFPlan <f> | The floorplan file and a power route data file next to it. Writes files. |
saveDesign <name>.enc | The whole database, as the checkpoint to return to. Writes files. |
editDelete -nets {<pwr_net> <gnd_net>} -shape RING | Deletes the ring wires of the nets so they can be rebuilt. Changes the database. |
editDelete -nets {<pwr_net> <gnd_net>} -shape STRIPE | Deletes the stripes of the nets. Changes the database. |
editDelete -nets {<pwr_net> <gnd_net>} -shape FOLLOWPIN | Deletes the followpin wires of the nets. Changes the database. |
editDelete -nets {<pwr_net> <gnd_net>} -shape COREWIRE | Deletes the core wires that sroute leaves outside the row area. Changes the database. |
editDelete -nets {<pwr_net> <gnd_net>} -shape BLOCKWIRE | Deletes the macro pin routes of the nets. Changes the database. |
deleteAllPowerPreroutes | Removes every power preroute from the floorplan. Changes the database. |
trim_pg -net {<pwr_net> <gnd_net>} -layer <layer> -pattern {<keep_trim_string>} -type stripe | Removes redundant stripes by a 0 and 1 pattern, based on IR drop evidence. Changes the database. |
reinforce_pg -auto_ir_fix preroute | Adds stripes between existing ones where Voltus reports IR drop violations. Changes the database; needs rail analysis. |
check_design -type place -out_file <f> | The placement prerequisite list, to be rerun in Chapter 6 once the grid is final. Writes a file. |
| Only if the block uses UPF | |
reportPowerDomain -file <f> | Power domain names, boxes, libraries and always-on status. Writes a file. |
reportPowerDomain -pgNet -file <f> | The power and ground nets of each domain. Writes a file. |
verifyPowerDomain -gconn | Checks that PG pins and tie connections inside each domain connect to that domain nets. |
verifyPowerSwitch -checkPlace -checkRowCoverage | Checks that power switches are placed and that every row is covered. |
reportPowerSwitch -outFile <f> | Every power switch instance with its location and pin connections. Writes a file. |