Innovus: Clock tree synthesis readiness Cheat Sheet

This stage checks the clock tree specification before CCOpt-CTS runs: clock definitions and propagation state, constants and clock gating, clock net routing rules, clock cell lists, skew targets, the clock tree specification itself, sinks and special pins, macro insertion delays, clock halos, and a final tool prerequisite check.

Sanity check cheat sheet

One row per command card. Read left to right: the check, the command that answers it, then what a healthy result, a result to review and a hard stop look like.

Card	Check and when	Command	Healthy	Review	Hard stop
K-01	Clock definitions and propagation state Before the specification	`check_timing -type clocks -verbose` `report_clocks` `getAnalysisMode -clockPropagation`	Every planned clock is listed and the clock findings are only ideal-clock warnings.	A clock_crossing finding with an owner, or a latency in the constraints that the clock plan does not list.	A planned clock is missing, a generated clock has no source, or the constraints propagate the clocks, which limits pre-CTS optimisation.
K-02	Constants, clock sense and gating Before the specification	`report_case_analysis -propagated` `report_clock_gating_check`	Each mode-select pin that steers a clock mux is constant in its mode, and each planned clock gate has a gating check.	A constant that exists only by propagation, so no constraint states the intent behind it.	A mux select left free in a mode, so the clock spreads into the datapath. K-07 then shows large path counts.
K-03	Clock net routing rules After K-02, before the specification	`get_ccopt_property route_type -net_type trunk` `add_ndr -name <ndr_name> -width_multiplier {<layers> 2} -spacing_multiplier {<layers> 2} -generate_via` `create_route_type -name <route_type> -non_default_rule <ndr_name> -top_preferred_layer <layer> -bottom_preferred_layer <layer> -shield_net VSS`	Each net type names a route type, and the track cost of each rule, as in the figure, fits the routing budget.	Extra spacing or shielding on leaf nets, which the reference says can consume too much routing resource.	A net type that the plan wants ruled has none, or a rule whose track cost the routing budget cannot afford.
K-04	Clock cell lists After K-03, before the specification	`get_ccopt_property buffer_cells` `report_ccopt_cell_filtering_reasons -cell_type buffer -file <f>` `set_ccopt_property buffer_cells {<buf_a> <buf_b>}`	The three lists are set on purpose, and every listed cell survives filtering in every view.	Some listed cells are filtered for a reason you accept, such as library trimming.	No usable inverter, buffer or clock gate remains for a clock tree, or a listed cell is missing in a view.
K-05	Targets and useful skew intent After K-04, before the specification	`get_ccopt_property target_max_trans` `getOptMode -opt_skew_ccopt` `getDesignMode`	The transition target is explicit and in known units, and the skew target and useful skew effort match the plan and the flow.	A target left at auto, where the plan accepts the SDC value or the automatic default.	A target in the wrong unit, such as 100 read as 10 ns, or one that check_design -type cts lists as a problem.
K-06	Clock tree specification After K-05	`create_ccopt_clock_tree_spec -file <spec.tcl>` `source <spec.tcl>` `get_ccopt_clock_trees *`	Each planned clock has a tree, each clock in each mode has a skew group, and nothing extra appears.	A tree for a redundant generated clock, or a skew group in a mode that the plan does not use.	A planned clock has no tree or skew group, or the specification was created before the special pins were final.
K-07	Sinks, special pins and convergence After K-06	`report_ccopt_clock_trees -list_special_pins -file <f>` `get_ccopt_clock_tree_sinks -in_clock_trees <clock_tree>` `set_ccopt_property sink_type ignore -pin <pin>`	Sink counts match the clock plan, every special pin is deliberate, and no sink has an unusually high clock path count.	Extra ignore pins that nobody asked for, or a few sinks with many paths that the plan explains.	Data pins counted as sinks, or large path counts from missing constants, which slow CCOpt and are not optimised as datapath.
K-08	Macro and sink insertion delays After K-06	`set_ccopt_property insertion_delay <value> -pin <macro_ck_pin>` `report_ccopt_pin_insertion_delays -file <f>`	Each macro clock pin has an insertion delay from the constraints or a recorded property, and its source is known.	Insertion delays on many ordinary sinks, which the reference says can raise clock area and power.	A macro clock pin with an internal clock delay and no insertion delay in the constraints or the properties.
K-09	Clock halos and protected clock objects After K-07	`report_preserves -dont_touch` `report_ccopt_cell_halo_violations -summary`	No clock instance violates a halo, and each dont_touch inside the clock tree is on the clock plan.	A few halo violations that the plan accepts, each with an owner.	A dont_touch on a cell or net inside the tree that CTS must resize or buffer, with no plan for it.
K-10	Tool prerequisite check Last check before CTS	`ccopt_design -check_prerequisites` `check_design -type cts -out_file <f>` `clock_opt_design -check_cts_config`	No design or clock tree configuration problem is listed and check_design reports no errors.	Warnings with an owner, such as a tight target that the project accepts.	The tool says it cannot run ccopt_design, or check_design finds errors, in which case the reference says the script stops.

Command cheat sheet

Legacy UI commands. Angle brackets are placeholders, and values shown are examples, not project limits.

Clock definitions and propagation state
`report_clocks`	The clocks from create_clock and create_generated_clock: waveforms and uncertainties.
`report_clocks -source_insertion -insertion`	The source and network insertion delays asserted on clock waveforms, as min:typ:max values.
`check_timing -type clocks -verbose`	Clock warnings with detail: missing clocks and generated clock sources, ideal clocks, crossings.
`check_timing -check_only {ideal_clock_waveform clock_not_propagated}`	Lists ideal clocks and ideal clocks that reach a timing check. Expected before CTS.
`report_case_analysis`	The ports and pins that carry a set_case_analysis constraint.
`report_case_analysis -propagated`	Adds the pins whose constant value comes from propagation.
`report_clock_gating_check`	Every clock gating check in the design, with its type.
`getAnalysisMode -clockPropagation`	How clock end points are treated, ideal or propagated. The setting is sdcControl, forcedIdeal or autoDetectClockTree.
`get_time_unit`	The time unit of the session, which decides how a bare number such as 100 is read by CTS properties.
Clock tree specification and skew groups
`get_ccopt_clock_trees *`	The names of every clock tree defined by the specification.
`get_ccopt_skew_groups *`	The names of every skew group. One is created per SDC clock per constraint mode.
`create_ccopt_clock_tree_spec -file <spec.tcl>`	Writes the specification as a Tcl script without running it. Without -file the trees are defined directly. Writes a file.
`source <spec.tcl>`	Runs the script, once. Until then no clock tree or skew group exists. Changes the database.
`delete_ccopt_clock_tree_spec`	Deletes skew groups and CTS configuration. Add -preserve_sink_insertion_delays to keep pin insertion delays. Changes the database.
`reset_ccopt_config`	Deletes the specification and every value set with set_ccopt_property. Changes the database.
Sinks, special pins and convergence
`get_ccopt_clock_tree_sinks -in_clock_trees <clock_tree>`	The pins that are sinks of the named clock trees.
`report_ccopt_clock_trees -list_special_pins -file <f>`	The clock tree report with stop, ignore and other special pins listed one by one. Writes a file.
`check_ccopt_clock_tree_convergence -warnthreshold <n>`	A warning for every sink with more than n clock paths leading to it.
`report_ccopt_clock_tree_convergence -num_worst_sinks <n> -file <f>`	A summary of convergence above sinks and the n sinks with the most clock paths. Writes a file.
`set_ccopt_property sink_type ignore -pin <pin>`	Marks a pin as an ignore pin so that it is not balanced. Set it before the specification is created. Changes a CCOpt property.
Routing rules and cell lists
`get_ccopt_property buffer_cells`	The buffer list for CTS. An empty list means CCOpt selects cells automatically.
`report_ccopt_cell_filtering_reasons -cell_type buffer -file <f>`	Why library cells of one type were filtered out for each clock tree. Writes a file.
`add_ndr -name <ndr_name> -width_multiplier {<layers> 2} -spacing_multiplier {<layers> 2} -generate_via`	Adds a non-default rule with wider wires and larger spacing. Changes the database.
`create_route_type -name <route_type> -non_default_rule <ndr_name> -top_preferred_layer <layer> -bottom_preferred_layer <layer> -shield_net VSS`	A route type that binds an NDR, a preferred layer pair and a shield net. Changes the database.
`set_ccopt_property -net_type trunk route_type <route_type>`	Applies a route type to all trunk nets. The same form works for leaf and top. Changes a CCOpt property.
`set_ccopt_property routing_top_min_fanout <n>`	Trunk nets above n sinks become top nets. Changes a CCOpt property.
`set_ccopt_property buffer_cells {<buf_a> <buf_b>}`	Sets the buffers CTS may use, overriding dont_use for them. Changes a CCOpt property.
Targets, insertion delays and useful skew
`get_ccopt_property target_max_trans`	The transition target. The value auto means the SDC target, or an automatic default, is used.
`get_ccopt_property target_skew`	The global skew target used by CCOpt-CTS.
`getOptMode -opt_skew_ccopt`	The useful skew effort: none, standard or extreme.
`report_ccopt_pin_insertion_delays -file <f>`	The pin insertion delays at clock tree sinks. Writes a file.
`set_ccopt_property target_max_trans 100ps -net_type leaf`	A transition target for leaf nets. 100ps is an example. Changes a CCOpt property.
`set_ccopt_property target_skew 50ps`	A skew target for CCOpt-CTS, ignored by ccopt_design without -cts. 50ps is an example. Changes a CCOpt property.
`set_ccopt_property insertion_delay <value> -pin <macro_ck_pin>`	The delay assumed inside a macro clock pin. Changes a CCOpt property.
`setOptMode -opt_skew_ccopt standard`	Sets the useful skew effort for ccopt_design and optDesign -postCTS. Changes a mode setting.
`setDesignMode -earlyClockFlow true`	Enables the early clock flow inside place_opt_design. Changes a mode setting.
Readiness checks and halos
`ccopt_design -check_prerequisites`	The setup, library and design checks of ccopt_design, without running CTS. It prints the problems found.
`clock_opt_design -check_cts_config`	The same prerequisite check for the place_opt_design V2 flow. It makes no changes.
`check_design -type cts -out_file <f>`	Checks of the clock tree definition, such as constraint targets and route types. Needs the specification loaded. Writes a file.
`report_ccopt_cell_halo_violations -summary`	Per clock, the clock instances with halos and the ones that violate them.
`report_preserves -dont_touch`	The dont_touch settings that affect optimisation, including those on clock cells and nets.
After CTS (for reference)
`ccopt_design -cts`	Clock tree synthesis only, without datapath optimisation or useful skew. Changes the database.
`report_ccopt_skew_groups -file <f>`	Insertion delay and skew per skew group and corner. Writes a file.