Chip Finishing and Design for Manufacturing in ICC2: A Mentor Guide

What chip finishing accomplishes, and where it sits

Here is what you are about to look at. Take the design that left the routing chapter. Zoom in until you can see individual wires on one metal layer. Now look at the space between the wires. In a normal routed block, most of that layer is empty. Chip finishing is the stage that fills a lot of that emptiness in, adds a second cut to vias that had one, moves some wires slightly further apart, closes every gap in every standard-cell row, and then proves the result can still be manufactured. It is the last implementation stage, and it is the first one whose customer is not another engineer. Its customer is a factory.

A beginner usually arrives here believing that routing was the last real step, and that finishing is cosmetic cleanup. That belief is comfortable and it is wrong. This chapter's job is to take it apart in Part 1, and then spend eleven more Parts proving it with measurements.

What this stage actually does

Concretely, by the end of this chapter you will be able to do eight things. You will confirm that a routed design is genuinely ready for finishing, rather than assuming the routing chapter's exit checklist is still true. You will choose the order in which finishing operations run, and explain why that order is not arbitrary. You will insert tap, boundary and filler cells, and say what each one physically provides. You will convert single-cut vias to redundant vias and read the conversion rate as a fraction rather than a verdict. You will reduce critical area with wire spreading and widening, and re-extract afterwards. You will measure metal density in windows, insert metal fill to correct it, and choose between fill types with reasons. You will measure what all of that did to timing, signal integrity and power, and repair what it broke. And you will run the signoff DRC loop and hand a manufacturable design to signoff with evidence attached.

As in every chapter of this guide, the goal is not memorizing flags. It is building the judgment a finishing engineer uses every day. Is this geometry manufacturable? What did making it manufacturable cost electrically? And is that cost affordable on this design, in this scenario, today?

Figure 1 — Chip Finishing and DFM in the ICC2 flow

Why “the wires are done” is not the same as “the chip can be built”

Routing finished with a design that is electrically correct. Every net connects what it should connect, and nothing shorts to anything else. Every wire obeys the minimum width and minimum spacing rules the router was given. Timing closes. That is a real achievement, and the routing chapter earned it.

It is also not sufficient. A foundry does not only ask whether your shapes obey spacing rules one pair at a time. It asks statistical and process questions about the layout as a whole. How much metal is on this layer, in this hundred-micron square? Is that fraction inside the range my polishing process can handle? Are there via cuts with no redundancy, where a single manufacturing defect opens a net? Are there pairs of wires close enough that a particle of the size my fab actually produces would bridge them? Are there wells with no tie to a supply rail? None of these questions is about connectivity, and routing answers none of them.

That is the gap this chapter closes. Everything in it exists because a manufacturing process is physical, imperfect and statistical, and a layout that ignores those three facts yields badly even when it is logically perfect.

The five things finishing adds, and what each one costs

Chip finishing is not one operation. It is a sequence of them, and each one has a distinct purpose and a distinct price. The table below is the map of the whole chapter.

Read the "Taught in" column as an order, not a list. Tap, boundary and filler cells go in first because everything after them treats the row as a fixed, continuous surface. Redundant vias and critical-area reduction come next because they move geometry that has not yet been made dense with fill, which keeps the change cheap to re-extract. Metal fill comes after both, because filling around geometry that is about to move would just mean filling it twice. Signoff DRC comes last because it is the only step that checks the result of everything before it, not a step with an outcome of its own.

Read the middle column and the right column together. Every row buys something real. Every row charges for it. The whole discipline of this stage is refusing to accept the left-hand benefit without measuring the right-hand cost.

Where the manual actually covers this

One scoping fact matters more than any other in this chapter, and it catches people out. The ICC2 User Guide covers this subject across two chapters, not one. Chapter 7, “Chip Finishing and Design for Manufacturing”, covers tap cells, boundary cells, antenna, redundant vias, critical-area reduction, MIM capacitors and filler cells. Metal fill gets a single line there. The real treatment of metal fill is forty pages away, in Chapter 8, “IC Validator In-Design”, because metal fill in this tool is done by an external signoff engine.

If you learn metal fill from User Guide Chapter 7 alone, you will learn almost nothing about it. This chapter is planned against both, and Part 7 says so explicitly.

After this chapter, you will be able to

• Reopen a routed checkpoint and verify, rather than assume, that the routing exit state is still true.
• Explain why finishing operations run in a particular order, and what goes wrong when they do not.
• Insert tap, boundary and filler cells, and describe the physical thing each one provides.
• Convert vias to redundant vias, read the conversion rate correctly, and explain every non-conversion.
• Reduce critical area with wire spreading and widening, and re-extract the nets you moved.
• Measure metal density in windows, interpret a worst-window number, and correct it with fill.
• Choose between floating and tied fill, and between pattern-based and track-based fill, with reasons.
• Measure what finishing cost in timing, signal integrity and power, and repair what it broke.
• Run the signoff DRC loop against a foundry runset and triage its results into fix, ECO and waive.
• Work through a stage-exit checklist and decide, with evidence, whether a design is ready for signoff.

The physics you need before you run anything

Here is the orientation for this Part. Everything that follows is about one idea: a chip is not drawn, it is manufactured, and manufacturing is a physical process with tolerances. A drawn rectangle becomes a real piece of metal with a thickness that varies, edges that are not exactly where you put them, and a chance of a stray particle landing on it. Every concept in this Part is a consequence of that gap between the drawing and the thing.

Vocabulary

These terms are used throughout the chapter. Each one is defined again, in context, where it first does real work.

Metal density, and the misconception that ruins it

Metal density is the fraction of an area that is covered by metal on one layer. That definition is simple, and almost every beginner gets the next step wrong.

The mistake is to think of density as a property of the chip, or of a layer. It is not. Density is a property of a window: a square region, typically somewhere between fifty and a few hundred microns on a side, whose size the foundry specifies. The checker slides that window across the layer, in steps smaller than the window itself, and computes density at every position. A layer passes only if every window passes.

This matters enormously, because averages hide exactly the failures you care about. A layer can average a comfortable thirty-four percent while containing one window at nine percent and another at eighty-one percent. Both of those windows fail. The average passes. If you check the average, you ship the failure.

The window size itself is not something you choose. It comes from the foundry's density-check deck, tuned to the polishing hardware that specific fab runs, and it is one of the few finishing parameters that never appears as a tool default because no single default could be right across every process.

Two windows on the same layer can fail for opposite reasons, and the fix for one can be the cause of the other. A window failing the minimum needs metal added. A window failing the maximum needs metal kept out. Treat every failing window on its own terms; a single global fill pass tuned to the worst minimum can just as easily push a different window over its maximum.

Figure 2 — Density is measured in a sliding window

Why density matters: chemical-mechanical polishing

Each metal layer is built by depositing metal, then polishing it back flat so the next layer has a level surface to sit on. That polishing step is chemical-mechanical polishing, or CMP. It uses a rotating pad and an abrasive slurry, and it removes material at a rate that depends on what is underneath.

Where there is very little metal, the pad presses down into the softer dielectric between the sparse metal lines and cuts a shallow trough. That is dishing. Where there is a great deal of metal packed together, the dielectric between the lines wears away faster than the metal does, and the whole region sinks. That is erosion. Both leave the surface lower than nominal, and both leave it uneven.

An uneven surface is not a cosmetic problem. It has four consequences that reach all the way back to your timing report.

• Resistance is wrong. The metal left behind after over-polishing is thinner than the model assumed, so its resistance is higher than extraction predicted.
• The error accumulates. The next layer is deposited onto a dip, so its own thickness varies too. Each layer inherits the unevenness of the one below.
• Lithography loses focus. Patterning an uneven surface costs depth of focus, which shows up as width variation, not only height variation.
• At the extreme, the net opens. An over-polished dense region can be polished through entirely, and the die is simply dead.

Figure 3 — CMP dishing and erosion

Metal fill

Metal fill is the answer to sparse regions. It is dummy metal: shapes added to a layer purely to raise local density, carrying no signal and connected to no logic. The tool places it, the foundry's rules constrain it, and it is completely invisible to your netlist.

It is not invisible electrically. A fill shape sitting beside a signal wire forms a capacitor with it. That capacitance is added to a net that timing analysis already signed off. This is the chapter's central fact and Part 7 and Part 8 are built around it.

Floating fill and tied fill

Fill shapes are either left unconnected, which is called floating fill, or connected to a supply net, usually ground, which is called tied or grounded fill. This is the most important fill decision a beginner meets, and the difference is not subtle.

A floating fill shape has no defined voltage. Whatever couples to it sets its potential, so it moves when its neighbours move. That makes it a path between two signal nets: net A couples charge onto the fill shape, the fill shape couples it onward to net B. The result is extra delay and extra crosstalk.

A tied fill shape is held at ground. It still adds capacitance to a nearby net, so the net still gets slower. But the other plate of that capacitor does not move, so the added load is predictable and it carries no noise between nets. Extraction handles it cleanly.

Tied fill therefore behaves better and costs more: it needs tie geometry, it loads the ground net, and it is more work for the fill tool and the router. Usually the foundry's deck settles the question. When it does not, that decision belongs with a senior engineer, not a default first move.

The fill-to-signal spacing dimensioned just below is not a fixed number picked once and forgotten. It is set through signoff.create_metal_fill.space_to_nets, the application option Part 7 walks through step by step, and it is the single value that trades fill density against coupling risk on every layer it touches. Widen it and coupling drops but so does density, which can push a marginal window below its minimum; narrow it and the reverse happens. Part 7 also covers the paired choice this section only names, floating versus tied, with the actual Nimbus-8 tie decision recorded per layer.

Both settings apply per layer, not once for the whole stack, because the trade lands differently on each one. A layer carrying mostly wide power straps can tolerate tighter fill-to-signal spacing than a layer carrying fine-pitch clock or data routing, where the same spacing buys much less density for much more coupling risk. Reading the figure below correctly means reading it as one layer's answer to that trade, not the whole stack's.

Figure 4 — Metal fill anatomy, and floating versus tied

Redundant vias

A via is the connection between two metal layers. It is made by etching a hole, called a cut, through the dielectric and filling it with metal. A cut is small, and the etch that makes it is one of the least reliable steps in the process. A cut that does not open properly, or that fills badly, is an open circuit.

A redundant via is a via with more than one cut doing the same job. If one cut fails, the other still carries the net. This is one of the cheapest yield improvements available, and it also lowers via resistance, which helps timing slightly.

It cannot always be done. Each cut needs metal extending past it on every side, on both layers, and that metal is the enclosure. A second cut needs a wider enclosure, and the wider enclosure needs room. Two situations commonly deny it. A neighbouring wire may sit too close for the wider enclosure to fit without violating spacing. Or the via may land on a cell pin, where the extra enclosure would block the only track by which a router can reach that pin.

Insertion is not uniform across a design. Clock nets and wide power straps tend to convert at close to one hundred percent, because they route on wide tracks with room to spare. The residual failures cluster on dense signal routing in the most congested regions, which is also where a defect would do the most damage. The conversion a design actually achieves matters more than its layer average suggests, so a via-mapping report broken out by net class is worth reading before accepting a single chip-wide number.

The via-mapping table itself is worth reading, not just its summary rate. It records, cut by cut, which vias converted, which were attempted and blocked, and which were never attempted because the tool's spacing check ruled them out before trying — three different outcomes a single percentage collapses into one number. A design with a high conversion rate built mostly from clock and power vias can still leave its most defect-sensitive signal nets single-cut, and the mapping table is the only place that distinction is visible.

Figure 5 — Redundant via insertion: converted, and the two ways it fails

Critical area and random defects

Manufacturing produces stray particles. A particle that lands on a layer can bridge two wires and cause a short, or sit in a wire and cause an open. Whether it does damage depends entirely on where it lands and how big it is.

Critical area is the area in which the centre of a particle of a given size must land for it to cause a failure. That is the whole definition. If two wires are far apart, only a very large particle can bridge them, and the region in which its centre must land is narrow. Move the wires closer and the same particle bridges them from a wider range of positions, so the critical area grows.

This is why critical area, rather than raw spacing, is the quantity the tool optimises. It converts a geometric fact into a yield number. Reducing it by thirty-five percent means roughly thirty-five percent fewer shorts from particles of that size.

Figure 6 — Critical area, made concrete

Tap cells, boundary cells and filler cells

Everything above this point has been about metal. This last group is about the silicon underneath it.

A CMOS standard cell sits in a well, and the well and the substrate around it must be held at a known voltage. If they are not, a parasitic structure inside the silicon can switch on and short VDD directly to VSS. That is latch-up, and it destroys the chip. A tap cell contains nothing but the connection that prevents it: the n-well tied up to VDD and the p-substrate tied down to VSS. The technology specifies a maximum distance any point may be from a tap, and finishing inserts taps at or below that interval.

A filler cell contains no function either. Its job is continuity. Standard cells have diffusion and well structures that must not simply stop at a cell edge with nothing beside them, so the gaps between placed cells are closed with filler cells of assorted widths until the row is continuous end to end.

A boundary cell, sometimes called an end-cap, does the same job at the places where a row genuinely ends: the left and right ends of each row, and anywhere the row meets a block edge, a macro or a voltage-area boundary. Those edges need a defined termination, not just filler.

None of the three carries logic, so none of them shows up in a timing report, and that is exactly why they are easy to under-budget for. On a real block the technology's maximum tap-to-tap distance sets a hard upper bound on spacing, but the actual placed interval usually comes in well under it, because filler and boundary insertion follow the row geometry the placer already committed to, not a clean grid drawn from scratch. The cost is area and a small leakage increase, paid once, before anything electrical in this chapter starts.

Order matters here for a reason that has nothing to do with any of the three cells themselves. Every later step in this chapter — redundant vias, critical-area reduction, fill — treats the standard-cell row as fixed background it routes and fills around. Insert taps, boundary and filler cells after those steps instead of before, and each one has to be re-checked against geometry that may already have moved, for no benefit: none of them interact electrically with metal density or via conversion at all. Row finishing goes first because it is the one group of operations every later step can safely assume is already done.

Figure 7 — Tap, boundary and filler cells in a standard-cell row

Antenna, one more time

The routing chapter introduced the antenna effect and fixed most of it. It appears again here for a specific reason, so the distinction is worth stating plainly.

During manufacturing, a wire is built before the layers above it exist. While it is partly built, it can act as a collector: charge accumulates on it from the plasma used in processing. If that wire is connected to a transistor gate and to nothing else that can bleed the charge away, the charge can punch through the thin gate oxide and damage the device permanently.

Routing fixed antenna violations while it still had freedom to reshape nets. What reaches chip finishing is the remainder: violations that finishing's own edits created, and violations on nets the router was told not to touch. Fixing them now is harder, because the route is closed and must be preserved. Part 5 covers it.

Signoff DRC, and why the router's DRC was not enough

The router checks its own geometry against its own internal rule model as it works. That model is fast and it is deliberately simplified, because the router has to consult it millions of times.

Signoff DRC is different in kind. It runs the foundry's actual rule deck, called a runset, through a dedicated verification engine. The deck contains rules the router's model does not carry at all: density rules, complex multi-layer conditional rules, antenna rules in their full form, double-patterning colouring rules, and rules that depend on the shape of a region rather than on a pair of edges.

Figure 8 — The finishing canvas

Verifying what routing actually handed you

Here is the orientation for this Part. Imagine taking delivery of a house from a builder. You have their sign-off sheet saying the roof is sound and the wiring is tested. Before you start knocking walls about, you go and look at the roof yourself. This Part is that walk-round. You reopen the routed checkpoint, re-measure every promise the routing chapter made, and find the one thing nobody measured at all.

How commands are shown in this chapter

Reopening the routing checkpoint

The routing chapter's exit state was saved as a named block. Chip finishing begins by opening it and confirming it opens cleanly.

open_block nimbus8_sens_tile_routed_postopt_v1
report_design -routing
check_routes -open_net true -drc true -antenna true

The fourteen readiness gates

The board below is the readiness check in full. The first ten gates re-verify what routing claimed. The last four are about what routing never looked at, and they are the reason this Part exists.

The gate that matters most

Gate eleven is deliberately classified REVIEW rather than PASS, and it is worth dwelling on why. Routing has no density check. It does not compute metal density, it does not report it, and it has no opinion about it. So the number that this chapter exists to fix has never been measured on this design.

A gate that has never been measured is not a passing gate. Classifying it PASS because nothing has complained would be exactly the habit this guide is written against. The required action is to measure it first, before changing anything, and to treat that first measurement as a baseline rather than as a result.

What you must have before you start

Beyond the design itself, finishing needs inputs that come from outside the tool. Not having them is the single most common reason a finishing run stalls on day one.

Save a recovery point before you change anything

Finishing is destructive in a specific sense. It adds thousands of cells and hundreds of thousands of shapes, and undoing that selectively is far harder than reopening a checkpoint. Save one now.

save_block -as nimbus8_sens_tile_pre_finish_v1

Why the sequence is not arbitrary

Here is the orientation for this Part. Think about decorating a room. You plaster before you paint, and you paint before you lay the carpet, because each step makes a mess of the one before it if you get the order wrong. Chip finishing has exactly that structure. Several of its steps modify geometry that other steps depend on, so running them in the wrong order means running some of them twice, or shipping a design where an earlier step's result was silently undone.

The order this chapter uses

The four orderings that go wrong

Rather than memorising the table, learn the four mistakes it prevents. Each one is common, and each one is recoverable but expensive.

The flagship view: one region, six steps

The two figures below are the most useful thing in this chapter. They show a single physical region — the same two nets, the same via positions, the same standard-cell row, at fixed coordinates — carried through all six finishing steps. Nothing moves between panels except what that step actually changes.

Each panel carries a status strip with six numbers: metal density on M4, the redundant via rate, critical area, the DRC count, setup slack in the worst-case corner, and total coupling capacitance relative to where it started. Read the first four as they improve. Read the last two at the same time.

The six steps run across four figures rather than one, because six panels at a size where the status strip stays legible do not fit on a single page, or even on two. Figures 9a and 9b, immediately below, carry the first three steps between them: 9a shows the region as routed and after critical-area reduction; 9b shows the redundant-via conversion that follows. Figures 9c and 9d, right after, carry the last three: 9c shows the row populated with boundary, tap and filler cells and then metal fill added; 9d shows the signoff geometry that results. Read all four figures as one continuous sequence, not as separate comparisons — panel 6, in 9d, is the same physical region and the same two nets as panel 1, in 9a, six steps later, and the status strip is what lets you confirm that nothing else about the region changed along the way.

Reading the last two fields at the same time, rather than one after the other, is the point of the whole exercise. Setup slack and coupling capacitance do not move together by coincidence: every panel where coupling rises is a panel where the fill tool or the router added something near the tracked nets, and setup slack is what pays for it. Across all six panels the region's setup slack falls from an as-routed +0.011 nanoseconds to a final +0.006, a drop of five picoseconds, and every picosecond of that drop lines up with a step that also moved the coupling number. Read the manufacturability columns for whether the region is ready to ship. Read the last two together for what shipping it cost.

Keep the units straight while you read: critical area, DRC count and the two rate fields are absolute or normalised counts, while setup slack is a time and coupling capacitance is a ratio to panel 1's own starting value, not an absolute farad number. That is deliberate. The chapter's argument is about the shape of the cost, not this one region's specific capacitance in femtofarads, and a relative number keeps the comparison honest across any region you check it against.

Figure 9a — One region through the chip-finishing sequence, part 1 of 4 (as routed; critical-area reduction)

Figure 9b — One region through the chip-finishing sequence, part 2 of 4 (redundant vias)

Figure 9c — One region through the chip-finishing sequence, part 3 of 4 (row finishing; metal fill)

Figure 9d — One region through the chip-finishing sequence, part 4 of 4 (signoff geometry)

What runs once, and what runs in a loop

Most of the order above runs once. Two parts of it do not, and recognising which is which saves a lot of confusion.

• Steps 2 to 10 run once on a healthy design. If you find yourself running fill three times, something upstream is wrong and repeating the step will not fix it.
• Step 11, extract and re-close timing, loops with its own repairs. Repairing a transition violation changes parasitics, which requires another measurement. Part 8 treats this as a measured loop with an exit condition.
• Step 12, signoff DRC, always loops. A repair can create a new violation, so every fix goes back through the check rather than to the exit. Part 9 draws this explicitly.

Finishing the silicon, not the metal

Here is the orientation for this Part. Everything so far has been about wires. Now look underneath them, at the rows of standard cells. After placement and routing, those rows are not solid. They have gaps, they have open ends, and the wells under them have no guaranteed connection to a supply. This Part closes all three, with three kinds of cell that between them contain no logic whatsoever.

Tap cells

A tap cell ties the n-well to VDD and the p-substrate to VSS. That is all it does. It contains no transistors that do anything useful.

Without it, the wells float. A floating well lets a parasitic bipolar structure inside the CMOS silicon switch on, and once it does it shorts VDD to VSS through a path that will not turn off until power is removed. That is latch-up, and it usually destroys the device. The technology specifies a maximum distance from any point in the design to the nearest tap, and that distance is not advisory.

create_tap_cells \
    -lib_cell nimbus8_lib/TAPCELL_X1 \
    -distance 18.0 \
    -pattern every_row \
    -skip_fixed_cells \
    -prefix TAP_

The four tap patterns

A uniform array is the common case, but three other shapes exist and each solves a different problem.

Boundary cells

A standard-cell row cannot simply stop. The diffusion and well structures inside the cells at the row's end need a defined termination, and so do the cells that sit against a macro, a block edge or a voltage-area boundary. Boundary cells, also called end-cap cells, provide it.

In ICC2 the rules come first and the insertion follows. You declare which library cell belongs at each kind of edge, and then run the insertion.

set_boundary_cell_rules \
    -left_boundary_cell nimbus8_lib/ENDCAPL_X1 \
    -right_boundary_cell nimbus8_lib/ENDCAPR_X1 \
    -top_boundary_cells nimbus8_lib/ENDCAPT_X1 \
    -bottom_boundary_cells nimbus8_lib/ENDCAPB_X1

compile_targeted_boundary_cells -all_targets

check_boundary_cells

Filler cells

Filler cells close what is left. Once taps and boundary cells are placed, every remaining gap between cells in every row is filled with function-free cells of assorted widths until the row is continuous.

Fillers go last among the cell-insertion steps for a simple reason: they consume whatever space is left, so anything that needs space must have taken it already.

create_stdcell_fillers \
    -lib_cells { nimbus8_lib/FILL_X8 nimbus8_lib/FILL_X4 \
                 nimbus8_lib/FILL_X2 nimbus8_lib/FILL_X1 } \
    -prefix FILL_

check_legality -chipfinishing auto

When fillers themselves cause DRC violations

A filler cell is a real piece of silicon with real geometry, and occasionally the filler that fits a gap dimensionally creates a design-rule violation against its neighbours. The tool provides a specific remedy rather than making you find them by hand.

remove_stdcell_fillers_with_violation \
    -check_only true

remove_stdcell_fillers_with_violation \
    -shorts_only true

create_stdcell_fillers \
    -lib_cells { nimbus8_lib/FILL_X2 nimbus8_lib/FILL_X1 } \
    -prefix FILLR_

Threshold-voltage-aware fillers

Some libraries require that the filler beside a cell match that cell's threshold-voltage flavour, because the implant regions must stay coherent. Where that applies, the rule is declared first and a different insertion command is used.

set_vt_filler_rule associates a set of filler cells with the threshold-voltage types they may abut, and create_vtcell_fillers then inserts fillers according to the threshold-voltage types of the neighbouring cells. Both are verified commands. Whether your library needs them is a library question, not a tool question, so check the library documentation before assuming either way.

Recall Figure 7: the row before and after finishing, with boundary cells at both ends, tap cells at a fixed interval and every gap closed by a filler cell — that is exactly the layout this Part just built, one operation at a time.

Antenna violations that survive into finishing

Routing closed the antenna violations it could. Two categories reach this stage anyway.

The first is violations that finishing itself created. Wire spreading and widening in Part 6 change the area of metal attached to a gate, and a net that was comfortably inside its antenna ratio can cross it after being widened. The second is violations on nets the router was told not to touch, where the fix had to be deferred.

The difference from routing is freedom. During detail routing, the router could reshape the net and place a diode wherever it liked, rebuilding the route around it. After detail routing, the route is closed and must be preserved, so the diode goes into the nearest free site and a stub connects it. That is cheaper to compute and worse for area and for timing.

On u_sens_tile, this is not a hypothetical count. Wire spreading and widening in Part 6 created 41 new antenna violations, all of them the first category above — nets whose widened or spread collector segment pushed the metal area on some gate past its ratio limit. None were carried over from routing, because routing's own antenna check ran clean before this chapter's handoff; the finishing chapter's edits are the entire cause. Every one of the 41 was fixed with a diode inserted after the fact, at the higher area-and-timing cost described above, because by the time critical-area reduction ran, the route the diode has to preserve was already closed.

This is also why the order in Part 4 puts antenna repair after critical-area reduction and redundant-via insertion rather than before them: those two steps are what creates most of the violations finishing itself is responsible for, so repairing antenna earlier would just mean repairing it again after they run.

The stub itself is not free. A diode placed at the nearest free site, rather than built into the net's own reshaped route, is reached by a short additional wire the router never planned for, and that wire adds both resistance and a small parasitic load the original timing closure never saw. On a net that was already close to its slack budget, forty-one of these stubs is forty-one small, avoidable timing costs stacked on top of the finishing chapter's own headline changes — which is one more reason the ordering in this Part exists: fewer violations reaching this stage means fewer stubs paying that price.

Figure 10 — Fixing antenna after the route is closed

check_routes -antenna true

create_diodes -options $antenna_violation_list

Buying yield with geometry

Here is the orientation for this Part. Both steps in it do the same thing in different ways: they make the layout more tolerant of manufacturing defects that have not happened yet. Nothing here fixes a bug. Everything here raises the fraction of manufactured die that come out working. Picture it as insurance bought with area and with a little timing margin.

Redundant vias

Via cuts are among the least reliable structures in the process. Adding a second cut in parallel means a single defective cut no longer opens the net. Via resistance drops as a bonus, which helps timing very slightly.

The insertion is a single command with an effort level, but the interesting part is what it does not convert.

add_redundant_vias \
    -effort high \
    -timing_preserve_setup_slack_threshold 0.020 \
    -timing_preserve_hold_slack_threshold 0.020

report_via_mapping

The via mapping table

Conversion is driven by a mapping table: for each single-cut via definition, which multi-cut definitions may replace it. The tool ships a default table derived from the technology, and you can add your own entries.

add_via_mapping declares a mapping with -from naming the via pattern to replace and -to naming the acceptable destination vias, with an optional -weight to prefer one over another and a -transform argument controlling whether flipped or rotated forms are allowed. report_via_mapping prints the table currently in effect, and remove_via_mappings deletes entries. Reading the table before insertion is worth the minute it takes, because a conversion rate that looks disappointing is often a mapping table that has no entry for the via type your design actually uses.

Reading the rate correctly

The redundant via rate is a fraction: converted cuts divided by convertible cuts. It is not a pass or fail verdict, and it will not reach one hundred percent on any real design.

On the Nimbus-8 sensor tile, 131,486 of 138,240 cuts converted, which is 95.1 percent. The 6,754 that did not convert break down into 4,102 blocked by adjacent geometry and 2,652 blocked by pin access. Those are geometric facts about a crowded layout, not tool failures.

Recall Figure 5: redundant via rate on u_sens_tile, 131,486 of 138,240 = 95.1%. The 4.9% that did not convert are cases 2 and 3 — blocked by geometry and by pin access — not tool failures.

Isolated vias

A separate command targets vias that remain single after the main pass. signoff_fix_isolated_via identifies isolated vias and inserts redundancy where it can, and it can also update track fill at the same time. It runs through the signoff engine, so it is Environment-specific: it requires IC Validator and a foundry runset, and what it achieves depends on both.

Critical-area reduction

The second half of this Part attacks a different defect mechanism. A particle landing between two wires shorts them if it is large enough to bridge the gap. A particle landing on a wire can break it if the wire is narrow enough.

Two operations address these. Wire spreading moves routed wires further apart where there is unused space beside them, shrinking the critical area for shorts. Wire widening makes wires wider where there is room, shrinking the critical area for opens and lowering resistance at the same time.

Both are opportunistic. They use space that the router left empty, and they do nothing where there is no space. On a congested design they achieve very little, and that is the correct outcome rather than a failure.

Recall Figure 6: critical area on M4 fell from 412 to 268 µm² per mm² after wire spreading — a thirty-five percent reduction, bought with geometry that must now be re-extracted and re-timed.

The cost, and why it is easy to miss

Wire spreading moves wires. Wire widening changes their cross-section. Both change resistance and capacitance, and both therefore change timing on nets that were closed.

The reason this is easy to miss is that the change is usually small and usually favourable. Spreading a wire away from its neighbour reduces coupling capacitance, which often improves timing slightly. A step that improves your numbers rarely gets audited. But the improvement is not uniform, some nets get slower, and the only way to know which is to re-extract.

set_parasitic_parameters -early_spec maxTLU -late_spec maxTLU

report_timing -delay_type max -nworst 20
report_constraint -all_violators

MIM capacitors

Metal-insulator-metal capacitors are decoupling capacitance built in the upper metal layers, between two plates separated by a thin insulator. They sit above the standard cells and stabilise the supply locally, which matters where switching current is high and the mesh alone cannot respond fast enough.

They are placed as an array of library cells across a region, in the same way as any other repeating cell.

create_mim_capacitor_array \
    -lib_cell nimbus8_lib/MIMCAP_X16 \
    -x_increment 12.0 \
    -y_increment 12.0 \
    -prefix MIM_

Everything this gate signs off is geometry that fill is about to bury. A track occupied by a widened wire or a converted via's wider enclosure is a track fill can no longer use. That is exactly why the order puts this gate before Part 7 rather than after it: metal density is measured against the geometry as it stands the moment fill runs, and every spread or widened shape this Part committed to becomes a permanent part of that measurement.

The step this chapter is really about

Here is the orientation for this Part. Go back to the image from Part 1: zoom in on one metal layer and look at the space between the wires. This Part measures how much of that space is empty, decides whether the answer is acceptable to the factory, and if it is not, fills some of it in with metal that does nothing. It is the largest single operation in chip finishing, it is the one with the biggest electrical consequence, and almost all of its parameters belong to the foundry rather than to you.

Where this is documented, and why that matters

User Guide Chapter 7, the chapter actually called “Chip Finishing and Design for Manufacturing”, gives metal fill one line and a cross-reference. The real treatment is forty pages away in User Guide Chapter 8, “IC Validator In-Design”.

The reason is structural. Metal fill in this tool is not performed by the placer or the router. It is performed by IC Validator, an external signoff verification engine, driven from inside ICC2 and using a foundry-supplied runset. Everything in this Part is therefore Environment-specific: the commands exist and are documented, but their behaviour, their parameters and their output depend on your IC Validator installation and your foundry's deck.

Step one: measure, before changing anything

The first thing to do is establish the baseline. Part 3 classified density as a REVIEW gate precisely because nobody had measured it, and this is where that action is discharged.

set_app_options -name signoff.report_metal_density.density_window -value 100
set_app_options -name signoff.report_metal_density.min_density -value 0.20
set_app_options -name signoff.report_metal_density.create_heat_maps -value true

signoff_report_metal_density

Reading a density heat map

A heat map shows density across the whole layer as colour, with the windows that fail highlighted. It is the fastest way to see whether a density problem is diffuse or local, and those two cases need different responses.

A diffuse problem — the whole layer is uniformly a little low — is the easy case, and ordinary fill fixes it. A local problem — most of the layer is fine and one region is empty — usually has a floorplan cause, such as a channel beside a macro that nothing routes through. Fill will fix the density number in that region, but it is worth knowing why the hole was there.

Recall Figure 2: the same region, nine windows, each judged on its own — average 34% PASSES, worst window 9% FAILS. That is exactly the report signoff_report_metal_density above is about to hand you.

Step two: choose the fill type

Two geometries are available, and they are not interchangeable.

Pattern-based fill tiles a foundry-defined pattern into empty space wherever it legally fits, ignoring the routing track grid. It reaches a density target in fewer shapes and matches the foundry's own fill deck most closely.

Track-based fill places every fill shape on a routing track, at track width, so the result looks like unused routing rather than tiled boxes. It costs more shapes for the same density. In exchange, a later ECO router can remove a whole fill track cleanly to make room for a new wire, where pattern fill has to be carved out around the new route.

The choice is not usually free-standing. A foundry deck often specifies pattern fill on the layers closest to the transistors, where its tighter match to the qualified process matters most, and leaves the choice open on upper routing layers, where ECO friction matters more than process match. Reading the deck's own layer-by-layer fill specification before setting this parameter chapter-wide avoids re-running the whole flow because one layer needed the other geometry.

Figure 11 — Pattern-based and track-based fill on the same region

Step three: choose floating or tied

Part 2 introduced the distinction and Figure 4 drew it. The decision belongs here.

Floating fill is simpler and cheaper. Its shapes are connected to nothing, so their potential follows whatever couples to them, and that makes each shape a possible path between two signal nets. The consequence is extra delay and extra crosstalk.

Tied fill holds every shape at VSS. It still adds capacitance, so nets still get slower, but the other plate of the capacitor does not move. The load is predictable and it carries no noise between nets.

In most flows the foundry's deck decides this, and there is no decision to make. Where it does not, prefer tied fill on the layers carrying your most sensitive nets, and accept the extra tie geometry as the price. That decision belongs with a senior engineer, not a default first move.

Step four: protect what matters, with timing-driven fill

Fill placed at the minimum legal spacing beside a critical net maximises density and maximises the coupling that net sees. Timing-driven fill leaves a wider keep-clear corridor beside nets you name, so those nets see less coupling.

It is important to be precise about what this does. Timing-driven fill does not fill less overall. It moves fill away from the nets you protected and places it elsewhere. The corridor comes out of the density budget in that region, and if the region was already marginal, the corridor can push a window below the minimum. You have then moved the failure rather than fixed anything.

Name nets for this corridor sparingly. Every net you protect widens the corridor somewhere, and a corridor list built from every net that merely touches the critical path, rather than the handful that actually sit on it, spends density budget protecting nets that were never at risk while leaving less of it for the ones that were. Part 8's own coupling-capacitance figures are for exactly this trade: the setup-slack recovery a named net gets back has to be checked against the density it cost elsewhere, not assumed.

Figure 12 — Timing-driven fill leaves a corridor

Choosing a corridor width is a negotiation, not a formula. A wide corridor protects the named net well but gives density nowhere to go except neighbouring windows, which can push one of them toward its own maximum. A narrow corridor protects less but stays local. Start narrow, re-measure, and widen only the corridors whose net still shows unacceptable coupling after the first pass.

Name nets sparingly. Every net in the protected list is a net whose local density has to go somewhere else, and a list built from an entire critical path rather than its worst few nets can starve a whole region. Part 8's dashboard is where an over-long list first becomes visible, as a cluster of windows sitting just above their minimum with no margin left.

Step five: insert the fill

set_app_options -name signoff.create_metal_fill.runset \
                -value /pdk/nimbus8/fill/nimbus8_fill.rs
set_app_options -name signoff.create_metal_fill.space_to_nets -value 0.120
set_app_options -name signoff.create_metal_fill.space_to_clock_nets -value 0.180
set_app_options -name signoff.create_metal_fill.max_density_threshold \
                -value { {M4 0.72} {M5 0.72} }
set_app_options -name signoff.create_metal_fill.fix_density_errors -value true

signoff_create_metal_fill \
    -mode add \
    -select_layers { M2 M3 M4 M5 M6 M7 } \
    -track_fill generic \
    -timing_preserve_setup_slack_threshold 0.020

Step six: measure again, and query the fill itself

Re-run the density measurement, and this time compare it against the baseline rather than against nothing.

signoff_report_metal_density

get_shapes -filter "layer_name == M4"

The density and fill compliance board

This is the most detailed board in the chapter, and it is the one to come back to.

Removing fill

Fill sometimes has to come out: a late ECO needs the space, or a repair in Part 9 requires it locally. signoff_create_metal_fill takes -mode remove for this, and there is also an ECO-aware path for removing track-based fill specifically, which frees whole tracks rather than carving shapes.

Removing fill lowers density. Any removal therefore requires re-measuring density afterwards, and the final density number in the exit state must come from a measurement taken after the last removal, not before it. Part 12 makes that the last step before stream-out for exactly this reason.

Paying the bill that Part 7 ran up

Here is the orientation for this Part. Everything up to now has been building. This Part is the audit. You re-extract the parasitics with all the finishing geometry in place, re-run every electrical check the routing chapter closed, and compare the answers with what you started from. If the numbers have not moved, the measurement is wrong, not the design.

Re-extraction comes first, and it is not optional

A timing report is only as good as the parasitics it was computed from. If you re-run timing without re-extracting, you get the old parasitics with a new timestamp, and it will look reassuring.

set_extraction_options -virtual_shield_extraction false
set_parasitic_parameters -early_spec maxTLU -late_spec maxTLU

report_qor -summary
report_constraint -all_violators

What finishing bought — the credit side

Before looking at the cost, record the benefit, so the two can be weighed against each other rather than discussed separately.

What finishing cost — the debit side

This is the board the chapter exists to produce. Read the Delta column first, then ask of each row whether that delta is affordable on this design.

Reading the two boards together

Taken alone, Dashboard 3 says finishing was a success: redundant via rate from zero to 95.1 percent, critical area down thirty-five percent, every row continuous, every well tied. Taken alone, Dashboard 4 says finishing cost five picoseconds of setup margin, briefly broke four paths and two transition limits, and raised total coupling capacitance by thirteen percent.

Both are true, and neither is the answer. The answer is that on this design the trade was worth making, and it was worth making because there was margin to spend. The routing chapter left +0.011 nanoseconds of setup slack. Finishing spent five picoseconds of it and left +0.006.

Now consider the same work on a design that entered finishing at +0.002 nanoseconds. The same fill would have taken it negative. The correct response there is not to skip fill, because density is not optional. It is to find timing margin before starting finishing, or to plan for timing-driven fill and a tighter corridor from the outset.

Repairing what finishing broke

Two rows on Dashboard 4 are REVIEW rather than PASS, and both were repaired rather than accepted. It is worth walking through how, because the repair is constrained in a way that postroute optimization in the routing chapter was not.

The four setup paths

Four paths went negative when re-extracted after fill. Total negative slack was −0.018 nanoseconds across all four, so none of them was badly broken.

The constraint is that the fix must not disturb the density you just achieved. Rerouting a net removes fill around the old route and requires fill around the new one, which changes local density in both places. So the repair is scoped as tightly as possible: resize drivers where that is enough, and only reroute where it is not.

report_timing -delay_type max -nworst 20 -max_paths 20 \
              -scenarios func_ss_0p72v_125c

report_constraint -all_violators

The two transition violations

Two nets on M6 exceeded maximum transition once fill capacitance was included. Both were fixed by upsizing the driver, which changes no routed geometry at all.

Notice why M6 and not a lower layer. M6 carries the ADC bus, which the routing chapter routed on M6 and M7 with a shielded non-default rule. Long wires with high capacitance and no slack to spare are exactly where an extra thirteen percent of coupling capacitance shows up first. Knowing which nets are most exposed before you fill is how you predict where the repairs will be.

Re-measure after repair

Every repair changes parasitics, so the loop closes only when a measurement taken after the last repair is clean. This is a measured loop with an exit condition, not a fixed number of iterations.

Power

Power moves too, and in two different ways.

Dynamic power rose from 1.87 to 1.94 milliwatts, a 3.7 percent increase. That is coupling capacitance: more capacitance to charge and discharge on every transition. It is a direct, expected consequence of fill and scales with how much fill you inserted.

Leakage rose from 0.097 to 0.103 milliwatts, a 6.2 percent increase. That is not fill. Fill leaks nothing. That is the thousands of filler cells, tap cells and boundary cells added in Part 5, each contributing a small leakage current. It is a cell-count effect, and it is one reason filler cell choice is not entirely free.

Passing this gate closes the electrical half of the chapter's argument, but it does not close the chapter. Every number Dashboard 4 just certified describes geometry that has not yet been checked against the foundry's actual rule deck — the router's own DRC and this chapter's density band are both internal approximations. Part 9 runs that outside check next, and because it is a separate tool reading the same geometry, a design that passes here can still fail there.

Checking against the foundry's rules, not the router's

Here is the orientation for this Part. Up to now every check has been the tool marking its own homework. Signoff DRC is the first time the design is checked against the foundry's actual rule deck, by a dedicated verification engine that was written for that job and nothing else. Think of it as sending the manuscript to the copy-editor after the spell-checker has already passed it.

Two things arrive at this Part already true, and it is worth stating them before the first check runs. Every metal-adding and metal-moving step in the chapter has finished, so the geometry being checked here is the geometry that will actually ship. And every earlier check in the flow, including the router's own DRC, has already passed. Signoff DRC does not repeat that work. It looks for what those checks were never built to see.

Running the check

set_app_options -name signoff.check_drc.run_dir \
                -value ./signoff_drc_run
set_app_options -name signoff.check_drc.read_layout_views -value true

signoff_check_drc \
    -error_data drc_run_1 \
    -check_all_runset_layers true

Triaging the results

A first signoff DRC run on a design that has never been through one will return a large number. On the Nimbus-8 sensor tile it returned 1,284. That number is not alarming by itself, because violations cluster: a handful of root causes typically produce most of the count.

Sort by rule name before doing anything else. A thousand violations of one rule is one problem. A thousand violations spread across two hundred rules is a different and much worse situation, usually meaning the wrong runset or the wrong process version.

Then triage every violation into one of three branches.

The three branches are not equally sized in practice, and knowing the shape in advance helps you plan the loop. Autofix typically clears the large majority of a first check's count in one pass, because most violations are local spacing and enclosure problems the tool's own repair rules were written to handle. The manual and ECO branch is small by count but large by effort, since each one needs a human decision about what may move. The waived branch should stay close to empty; a rule waived for convenience rather than for a genuine, documented exception is a rule you have quietly stopped checking.

Part 10's worked example shows the shape in real numbers. The first check on u_sens_tile returned 1,284 violations. A scoped autofix pass cleared 1,094 of them immediately — the large majority the paragraph above describes. Of the 190 that remained, 174 were cleared by a second, narrower autofix pass targeting the specific rule families still open, and the last 16 needed a scoped route ECO each. Zero were waived. Three check-and-fix loops closed the count to zero in total, which is itself a data point: a loop that has not converged after three or four passes is usually not going to converge on autofix alone, and is a sign to move violations into the manual branch rather than keep re-running the same repair.

Figure 13 — The signoff DRC loop

Notice what the loop does not do: it never assumes a repair worked. Every branch, including the one waived with the foundry, ends by returning to the top and counting again. That discipline is what makes the exit condition trustworthy. A count of zero at the end of this loop means zero on the geometry that exists right now, not zero on the geometry that existed before the last repair.

A loop needs a stop condition beyond zero violations, because a hard violation that no repair touches will otherwise run forever. Bound the iteration count before the first run, watch whether the count is falling on each pass, and treat a loop that stops falling before it reaches zero as a design question, not a tool setting to push higher.

Autofix

set_app_options -name signoff.fix_drc.max_errors_per_rule -value 2000
set_app_options -name signoff.fix_drc.fix_detail_route_drc -value true

signoff_fix_drc \
    -start_repair_loop 1 \
    -max_number_repair_loop 3 \
    -select_rules { M4.S.1 M5.S.1 V4.EN.2 }

Double patterning

On processes that use double patterning, some layers are manufactured in two exposures, and every shape on such a layer must be assigned to one of two masks. Shapes too close together must be on different masks. Sometimes the geometry makes that impossible, because a loop of shapes forces a contradiction. That is an odd-cycle violation.

An odd cycle cannot be fixed by recolouring, since no colouring exists. It can only be fixed by changing the geometry so the cycle is broken. The tool supports odd-cycle fixing as part of the signoff DRC repair flow, and it is worth knowing this class exists so that a violation which resists every ordinary repair is recognised rather than retried.

PG augmentation

Power and ground augmentation adds extra supply metal after routing, into space that turned out to be free. More supply metal lowers IR drop and improves electromigration margin, and it costs nothing in function.

It belongs before fill in the order, because it adds metal and therefore density. Filling first and augmenting afterwards can push windows over the maximum.

The metal it adds is not automatically free of the antenna and critical-area concerns the rest of this chapter spends so much effort on, since it is still real shapes on real layers, connected to a net that genuinely matters — the supply mesh. A guided or timing-driven augmentation pass that targets only the regions actually short of margin, rather than a standard pass applied everywhere, keeps that added metal from becoming density this chapter's own fill budget then has to make room for. A standard pass is the right default only when no IR-drop or electromigration report yet exists to guide a narrower one; once that report exists, use it.

set_app_options -name signoff.create_pg_augmentation.power_net_name -value VDD
set_app_options -name signoff.create_pg_augmentation.ground_net_name -value VSS

signoff_create_pg_augmentation \
    -node generic \
    -mode add

Isolated via repair

Part 6 left 6,754 vias unconverted. signoff_fix_isolated_via takes a second pass at them through the signoff engine, and can update track fill at the same time so that freeing a track for a redundant cut does not leave a density hole. On the Nimbus-8 sensor tile it reduced the count from 6,754 to 6,318.

That is a 436-via improvement, and then the numbers stop moving. The remaining cases need routed geometry to move. At that point the right answer is to stop and record the residual, which is what Dashboard 3 and Dashboard 5 both do.

Chip finishing on u_sens_tile, end to end

Here is the orientation for this Part. Everything so far has been the method. This is the method applied once, to a real partition, in order, with the numbers written down at every step. Follow it as a narrative rather than a recipe: the interesting content is the decisions, not the command lines, which you have already seen.

The design, and what it inherits

The teaching design is Nimbus-8: 9.90 million standard cells, 72 SRAM macros, one DDR PHY hard macro, a 3.20 by 3.20 millimetre core, and four clocks at 1.60 gigahertz, 1.10 gigahertz, 800 megahertz and 200 megahertz.

As in the routing chapter, the worked example runs on one named partition rather than the whole design. That partition is u_sens_tile, the sensor-interface tile carrying the ADC input bus: 46,200 standard cells, 2 of Nimbus-8's 72 SRAM macros, 0.70 by 0.62 millimetres, which is 0.434 square millimetres, at 79.6 percent utilization.

Step 1 — Reopen, re-verify, save a recovery point

The checkpoint opened cleanly, with two informational messages and no warnings. All three connectivity and rule checks returned zero, matching the routing exit record exactly.

Density was recognised as unmeasured and classified REVIEW on Dashboard 1, with the action deferred to step 8. The pre-finishing recovery point nimbus8_sens_tile_pre_finish_v1 was saved before anything else ran.

Verdict: PASS — 13 PASS, 1 REVIEW with a stated action, 0 BLOCKER.

Step 2 — Tap cells

The technology specifies a maximum well-tie distance of 20.0 microns. Taps were inserted at 18.0 microns with the every_row pattern, giving margin against the limit rather than sitting on it.

4,208 tap cells were inserted, prefixed TAP_. The maximum realised tie distance was 18.0 microns, comfortably inside the 20.0 micron rule. No tap walls or meshes were used: this partition has one voltage domain and no analogue neighbour, so the uniform array is the right and cheapest answer.

Verdict: PASS.

Step 3 — Boundary cells

Boundary cell rules were declared for left, right, top and bottom edges, and then compiled across all targets. 1,964 boundary cells were inserted, and check_boundary_cells returned zero violations.

Boundary cell insertion also created routing guides and placement blockages along the row ends, as expected. They were left in place.

Verdict: PASS.

Step 4 — Critical-area reduction

Wire spreading moved 18,340 segments, none by more than two tracks. Wire widening widened 7,115 segments, restricted to M4 through M7. M2 and M3 were excluded because their density was already healthy and widening there would have pushed windows towards the maximum for no yield gain.

Critical area on M2 through M7 fell from 412 to 268 square microns per square millimetre, a 35 percent reduction.

Every moved or widened net was re-extracted. Three nets changed setup slack by more than five picoseconds, and all three remained positive. The worst was SIG_CRIT_038 at +0.014 nanoseconds, down from +0.021. That is a real cost and it was recorded rather than absorbed.

Verdict: PASS.

Step 5 — Redundant vias

The via mapping table was reported first and found to contain entries for every via definition the design uses, so no custom mappings were added.

Insertion ran at high effort with setup and hold preserve thresholds of 0.020 nanoseconds, so vias on nets inside that margin were left alone. 131,486 of 138,240 cuts converted, a rate of 95.1 percent. Of the 6,754 that did not, 4,102 were blocked by adjacent geometry and 2,652 by pin access.

Verdict: PASS, with the residual recorded.

Step 6 — Antenna repair

Wire widening in step 4 increased the metal area attached to several gates, and check_routes -antenna true found 41 new violations on nets that had been clean at routing exit. All 41 were on widened M4 and M6 segments, which is exactly where the widening ran.

Diodes were inserted for all 41. Because the route is closed, each diode went into the nearest free site with a stub connecting it, rather than abutting the gate as it would have during routing. This ran before filler insertion, so free sites still existed. A re-check returned zero.

Verdict: PASS. Note that this step existed only because step 4 happened. That is the order dependency from Part 4 doing its job.

Step 7 — Filler cells

Fillers were inserted from a descending width list, closing every remaining gap. check_legality -chipfinishing auto returned zero violations.

31 fillers were then found to create design-rule violations against their neighbours. They were removed with remove_stdcell_fillers_with_violation and the gaps re-filled with narrower cells under a distinct prefix. A re-check returned zero.

Verdict: PASS.

Step 8 — Density baseline

This is where Dashboard 1's REVIEW gate is discharged. Density was measured for the first time on this design.

Four of nine layers had at least one window below the minimum. The worst was M9, at 4.4 percent against a 20 percent minimum. M8 was next at 6.1 percent, then M4 at 9.2 percent and M5 at 11.7 percent. No layer exceeded its maximum anywhere.

The pattern is exactly what a heat map would predict. The upper layers are the emptiest, because routing uses them least. The middle layers are healthier. Nothing was surprising, which is itself worth recording: a surprising density baseline usually means a floorplan problem rather than a fill problem.

Verdict: BLOCKER until fill. Four layers are outside the band and the design cannot be taped out in this state.

Step 9 — PG augmentation

Augmentation ran before fill, so that fill would see the augmented mesh and size itself against it. Extra VDD and VSS metal was added into space that routing had left free, and the result was verified to contain no dangling augmentation shapes and to leave PG connectivity unchanged.

Verdict: PASS.

Step 10 — Metal fill

Three decisions were made before the command ran, and each was written down.

• Fill type. Track-based on M2 through M7, where ECO routing is likely. Pattern-based on M8 and M9, where routing is sparse and ECOs rarely reach.
• Tie. Floating on M2 through M5, tied to VSS on M6 through M9. The foundry deck permits both; M6 and M7 carry the shielded ADC bus, and tied fill there keeps the coupling those nets see predictable.
• Timing-driven corridor. Enabled, with a wider keep-clear corridor beside the 42 NDR_WIDE_2X nets and the 16 ADC-bus nets.

After insertion, all nine layers were inside the band. M4's worst window rose from 9.2 to 27.1 percent, M9's from 4.4 to 21.3 percent. The worst window on the whole design is now M9 at 21.3 percent against a 20 percent minimum, which is inside the band with little margin and is worth noting in the handoff.

The timing-driven corridor was then checked against the density it cost. M6, which carries the corridor, came out at a 24.8 percent worst window against a 22 percent minimum. The corridor was affordable. Dashboard 2's one REVIEW row is exactly this check, and it was re-classified PASS once the number came back.

Verdict: PASS. Density compliant on every layer.

Step 11 — Re-extract and re-close timing

Parasitics were re-extracted with the fill in place, verified by querying fill shapes back out of the block first.

Setup worst negative slack on func_ss_0p72v_125c fell from +0.011 to +0.004 nanoseconds, and four paths went negative with a total negative slack of −0.018 nanoseconds. Two nets on M6 exceeded maximum transition. Coupling capacitance rose 13 percent overall. Hold improved very slightly, from +0.019 to +0.021 nanoseconds, which is the expected direction: extra capacitance slows data paths, and slower data helps hold.

Repairs were scoped tightly. Both transition violations were fixed by upsizing drivers, which moves no routed geometry. Three of the four setup paths were fixed by resizing. The fourth needed a short reroute on one segment, and because that reroute disturbed fill locally, density was re-measured afterwards on the affected layer and confirmed still inside the band.

Final state: WNS setup +0.006 nanoseconds, TNS setup 0, WNS hold +0.021 nanoseconds, TNS hold 0, zero transition and capacitance violators, zero crosstalk violators.

Verdict: PASS, with two REVIEW rows on Dashboard 4 recording what had to be repaired.

Step 12 — Signoff DRC

The first run returned 1,284 violations. Sorted by rule, 1,102 of them were two rules: a fill-to-signal spacing rule on M4 and M5, and a via enclosure rule on V4. Both are exactly what steps 5 and 10 would be expected to produce.

Autofix was run, scoped to those two rule families only, with the repair loop bounded at three. It cleared 1,094. The remaining 190 were triaged: 174 were fixed by a second, narrower autofix pass, and 16 needed scoped route ECOs.

Three check-and-fix loops were needed in total. The third returned zero. No waivers were used.

Because autofix had removed fill in places to make room, density was re-measured after the last repair. All nine layers were still inside the band, with M9's worst window at 21.3 percent unchanged.

Verdict: PASS.

Step 13 — Isolated vias, then save and stream out

signoff_fix_isolated_via reduced the unconverted count from 6,754 to 6,318. Further passes achieved nothing without moving routed geometry, so the count was accepted and recorded.

The final block was saved as nimbus8_sens_tile_finished_v1 and confirmed to reopen cleanly. GDSII was written, and the exact layer map file used was recorded alongside it in the handoff.

Verdict: GO.

Nothing in the checkpoint name or the GDSII file states any of this on its own. The evidence that nimbus8_sens_tile_finished_v1 is actually ready lives in the thirteen verdicts above it, and in the reports each one cites. That is what a handoff record is for: not the file, but the trail that says the file may be trusted.

The layer map deserves the same scrutiny as the geometry itself. It is the only place that says which drawn layer becomes which mask, and a design and a layer map that individually check out can still produce a wrong GDSII together if the map does not match the tape-out the geometry was actually signed off against. Recording the exact map file alongside the checkpoint, not just its name, is what lets a downstream consumer confirm they are opening what this handoff actually describes.

Figure 14 — What leaves the tool at stream-out

The whole example in one table

Do it yourself, and get it wrong once on purpose

Here is the orientation for this Part. Reading about a cost is not the same as watching a number move. This lab is built so that you break something deliberately in the middle of it, see the consequence in a report, and then fix it. That is the part you will remember.

Exercise 1 — Establish the baseline

Open a routed, timing-closed block. Before running any finishing command, record six numbers: worst negative slack for setup in your worst corner, worst negative slack for hold, total negative slack for both, dynamic power, and leakage power. Save them in a file, not in your head.

Close with: a file containing six numbers and the checkpoint name they came from. PASS if the file exists before any finishing command has run.

Exercise 2 — Save a recovery point

Save the block under a name that states the design, the partition, the stage boundary and a version. Then close it and reopen it from that name, to prove it reopens.

Close with: a checkpoint that reopens with no unexplained message. PASS if reopening produces the same report output as before saving.

Exercise 3 — Insert taps, and check the interval you chose

Find the maximum well-tie distance in your technology file or library documentation. Do not guess it. Insert tap cells at a distance comfortably inside it, with a prefix.

Then count the taps you inserted and check the count against the arithmetic: core area divided by the square of the tap pitch, roughly. If the count is wildly different from that estimate, something is wrong with the pattern or the voltage-area argument.

Close with: a tap count, the interval used, and the technology limit it was checked against. PASS if the interval is inside the limit and the count is within about twenty percent of the estimate.

Exercise 4 — Insert boundary cells and fillers, in the right order

Declare boundary cell rules, compile them, and check. Then insert fillers from a descending width list. Then check legality with the chip-finishing option.

Close with: zero from the boundary cell check and zero from the legality check. PASS on both zeros.

Exercise 5 — The deliberate mistake

This is the exercise that teaches the chapter. You are going to do step 7 and step 11 of Part 4's order in the wrong sequence, on purpose.

1. Re-extract parasitics and record worst negative slack for setup. Call this number A.
2. Now insert metal fill, with whatever settings your foundry deck permits.
3. Without re-extracting, re-run your timing report. Record worst negative slack. Call this B.
4. Now re-extract, and run the timing report again. Record worst negative slack. Call this C.

You will find that B equals A, and C does not. That is the whole lesson. Re-running timing without re-extracting produced a clean-looking report for a design that had already changed. Nothing warned you. The report was not wrong about the parasitics it was given; it was given the wrong parasitics.

Close with: three numbers, A, B and C, and one sentence explaining why B is useless. PASS if C differs from A and you can say why.

Exercise 6 — Measure density before and after

Reopen your recovery point so the deliberate mistake is discarded. Measure density before inserting any fill and record, per layer, both the layer average and the worst window.

Then insert fill and measure again. Build a small table with four columns: layer, average before, average after, worst window before, worst window after.

Look at which column moved most. On almost every design it will be the worst window, not the average.

Close with: the table. PASS if every layer's worst window is inside the foundry band, and you can name which layer had the least margin.

Exercise 7 — Price the timing-driven corridor

Pick your five most timing-critical nets. Insert fill twice: once without a timing-driven corridor, once with one protecting those nets.

Record, for both runs, the worst negative slack on those five nets and the worst window density on the layers they run on.

You have now measured the trade directly: how much density the corridor cost, and how much slack it bought. Decide whether you would take it.

Close with: four numbers and a one-sentence decision with a reason. PASS if the decision names both the density cost and the slack gained.

Exercise 8 — Write the exit state

Produce the handoff record. It must contain per-layer density after fill, the redundant via rate, critical area before and after, the fill type and tie choice per layer, signoff DRC status with any waivers named, final timing per scenario, and the saved checkpoint name.

Then give it to somebody who did not do the work and ask whether they could start the next stage from it. If they have to ask you a question, the record is incomplete.

Close with: the record, and a named checkpoint that reopens. PASS if a colleague can read it without asking you anything.

Lab close-out

A lab result of eight PASS means you can run this stage. A REVIEW on exercise 5 or 6 means the two most important ideas in the chapter have not landed yet, and those two are worth repeating before moving on.

The handoff to signoff

Here is the orientation for this Part. Everything the chapter has built now has to leave the tool and go to people who cannot ask you questions: a verification team, a mask shop, a foundry. This Part decides whether it is ready, writes it out, and records what was written and how.

The final ordering, and why density is measured last

Two things happen near the end that change density, and both happen after the fill step. Signoff DRC autofix can remove fill to make room for a repair. A scoped route ECO in Part 8 removes fill along the old route.

So the density number that goes into the handoff must come from a measurement taken after the last of those, not from the measurement taken when fill was inserted. This is the single most common way a handoff record ends up containing a number that was true an hour earlier.

The same logic applies to every other number in the handoff, not only density. Timing, power, LVS readiness, and the antenna check all need to be measured after the last operation capable of moving them, or the record is a snapshot of a design that no longer exists. The sequence below exists to put every measurement after everything that could invalidate it.

Treat the order below as load-bearing, not as a checklist to be run in any convenient sequence. Moving a single line ahead of an operation it depends on reproduces exactly the density-after-augmentation and timing-before-fill mistakes Part 4 spent its whole ordering table warning against, at the one point in the flow where there is no later step left to catch it.

signoff_check_drc -error_data drc_final

signoff_report_metal_density

check_lvs -checks { short open floating_routes }
check_legality -chipfinishing auto
check_boundary_cells
check_routes -antenna true

report_qor -summary
report_power

save_block -as nimbus8_sens_tile_finished_v1

The go / no-go board

Stream-out

Stream-out writes the design as GDSII, which is the format the rest of the world reads. It is a translation, and the layer map is the dictionary.

The layer map translates the tool's internal layer names into the foundry's GDSII layer numbers and datatypes. One line in it matters more than the rest: dummy fill must be written on its own datatype, distinct from signal metal on the same layer.

set_app_options -name signoff.physical.layer_map_file \
                -value /pdk/nimbus8/gds/nimbus8_layermap.map

write_gds -fill include \
          -hierarchy all \
          -compress \
          nimbus8_sens_tile_finished_v1.gds

Recall Figure 14: the stream-out handoff — block contents, layer map, downstream consumers — and the failure it exists to prevent: fill written on the same datatype as signal metal passes DRC and fails LVS.

The exit state handed to Chapter 7

Chapter 7, Hierarchical Implementation, starts from this state. Everything it needs is below.

Checking that it landed

Here is the orientation for this Part. The questions below are the ones an interviewer actually asks about this stage, and the ones you will ask yourself six months from now when something goes wrong. Try to answer each one before reading on.

Reader questions

Flashcards

Self-check

You are ready to leave this chapter when you can do all of the following without looking anything up.

• State why a passing density average can hide a failing layer, and say which number to ask for instead.
• Explain how fill changes timing without touching a signal wire.
• Give the order of the finishing operations, and name the dependency that fixes each position.
• Name the two reasons a redundant via cannot be inserted, and say why a 95 percent rate is the right answer.
• Define critical area in one sentence, without using a formula.
• Say what tap cells, filler cells and boundary cells each physically provide.
• Explain why antenna violations can appear during chip finishing on nets that were clean at routing exit.
• Describe the signoff DRC loop, including why every fix returns to the check.
• List what has to be re-measured after a route ECO made during finishing, and say why.
• Name every value in the exit state, and say which downstream stage needs each one.