Multi-Mode Multi-Corner (MMMC) Timing Signoff: Complete Guide
Modern ASICs must function correctly across dozens of operating modes (functional, scan shift, scan capture, BIST, sleep) and environmental process, voltage, temperature, and RC parasitic corners. Multi-Mode Multi-Corner (MMMC / MCMM) ensures clean timing closure without silicon escapes.
1. Modes vs Corners: The Fundamental Distinction
A classic interview trap is confusing an operating mode with an operating corner:
| Concept | Definition | Determined By | Examples |
|---|---|---|---|
| Constraint Mode | Design functional state and clock behavior | Design intent & SDC files | Functional, Scan Shift, Scan Capture, High-Speed Turbo, Low-Power Standby |
| Process Corner | Silicon fabrication speed & threshold voltage | Foundry fab variation | Fast-Fast (FF), Slow-Slow (SS), Typical-Typical (TT), Fast-Slow (FS) |
| RC Parasitic Corner | Interconnect wire resistance & capacitance | Interconnect BEOL variations | Cworst (max C, min R), Rworst (max R, min C), RCworst, RCbest |
2. Analysis Views & Scenario Definition
An Analysis View (known as a Scenario in Synopsys PrimeTime and ICC2) connects one logical constraint mode with one physical delay corner:
# Example PrimeTime MCMM Scenario Setup:
create_scenario func_ss_cworst
set_operating_conditions -analysis_type on_chip_variation SS_0P7V_125C
read_parasitics -format SPEF -corner Cworst design.spef.gz
read_sdc functional_mode.sdc
3. Why Single-Corner Signoff Fails
Engineers historically checked setup only at SS / 125C / Cworst and hold only at FF / -40C / Cbest. In modern sub-7nm FinFET nodes with temperature inversion, this approach causes silicon failures:
- Temperature Inversion: Lower temperatures (e.g. -40°C) produce slower cell delays than 125°C at ultra-low supply voltages due to threshold voltage increases dominating mobility gains.
- RC Interconnect Dominance: Paths with long metal routes may have worst setup slack at
SS / Rworstrather thanSS / Cworst.
6. MMMC Interview FAQs
What is the fundamental difference between an operating mode and a corner?
A mode represents design behavior defined by SDC constraints (e.g. functional mode vs scan test mode). A corner represents physical manufacturing variation and environmental operating conditions (e.g. Slow-Slow 0.7V -40C with Cworst parasitics).
What components constitute an analysis view (scenario)?
An analysis view links a specific Constraint Mode (SDC file) with a specific Delay Corner (composed of Library Timing Corner .lib and Parasitic RC Corner SPEF/TLU+).
Why does fixing a setup violation in one view often cause a hold violation in another?
Upsizing a driver to fix setup at SS corner speeds up the path across all corners, which can violate minimum delay hold requirements at the FF early corner where delays are already minimal.