What this chapter covers

No chip is an island. This chapter is timing at the boundary: system-synchronous interfaces that share a clock versus source-synchronous interfaces that forward a clock with the data, how input/output delay budgets split across two chips or blocks, virtual clocks, and how to verify the shared contract so independently designed pieces still work together.

Use it for memory interfaces, buses, GPIO, chip-to-chip links, and hierarchical block boundaries. Interface bugs are integration-level and expensive: a block that is “clean internally” can still miss its I/O budget.

Worked example

A system-synchronous input budget: external launch clock-to-Q + board delay + your set_input_delay must leave enough on-chip slack to the first flop. A source-synchronous output instead defines a generated or virtual clock for the forwarded strobe and times data against that strobe, not against the core clock alone.

A common misconception

Using the core clock as the only I/O reference when the board uses a forwarded clock, or putting all of the uncertainty on one side of the interface so the two teams’ budgets no longer add up. Unconstrained ports look like internal timing is done.

Sample interview answers

What does set_input_delay represent? How much of the period is already consumed before data arrives at the port — the external world’s launch path, referenced to a (possibly virtual) clock.

When do you need a virtual clock? When the external launch or capture clock is not a pin in this netlist, but I/O paths still need a reference for input/output delay.

How is source-synchronous timing different? Data is checked against a forwarded strobe (often a generated clock) rather than assuming the receiver shares your core clock.

The paid chapter works system- versus source-synchronous diagrams, virtual-clock SDC, budget spreadsheets, and interview questions for interface STA.

Constraints: I/O and port delays · Next: Robust verification · Related: set_input_delay, set_output_delay

💡 Key Technical Topics Covered

  • System Synchronous vs Source Synchronous Interfaces
  • Virtual Clock Definition & Usage
  • Input Delay & Output Delay Calculations
  • Board Trace Delay & Clock Center Alignment

🎯 VLSI Physical Design Interview Questions Addressed

  • What is a virtual clock and when should you use it?
  • How do you calculate set_input_delay for an external memory interface?
  • Explain source synchronous timing verification in high-speed interfaces.