Differential Pairs and Op-Amps

The single-stage amplifiers of lesson 3 have two weaknesses: their output level drifts with any disturbance on the input or supply, and an active-loaded stage has no natural way of setting its own DC level. The differential pair addresses both. It amplifies the difference between two inputs and rejects what they have in common, and it is the input stage of nearly every operational amplifier, comparator and many receiver circuits.

This lesson builds from the differential pair to a five-transistor operational transconductance amplifier (OTA), then to a two-stage op-amp, and ends with the frequency-domain questions every feedback amplifier raises: gain-bandwidth, compensation and phase margin.

Reading time: about 9 minutes.

5.1 The differential pair

Let us consider two matched NMOS transistors M1 and M2 whose sources are tied together and fed by a tail current source ISS. Each drain connects through a load RD to VDD. The inputs are vin+ and vin−, and it is useful to rewrite them as two components:

• Differential-mode input vid = vin+ − vin−, the signal we want.
• Common-mode input vic = (vin+ + vin−)/2, the average, which usually carries noise, supply coupling or a DC offset we want to ignore.

With no differential input, ISS splits equally, ISS/2 through each side. A small differential input steers current from one side to the other: one drain current rises by gm·vid/2, the other falls by the same amount, and the shared source node does not move to first order. Thus, each half behaves like the common-source stage of lesson 3, and the differential output gain is

Adm = (vout+ − vout−) / vid = gm · RD          (5.1)

where gm is the transconductance of each device at ID = ISS/2, and ro is assumed much larger than RD. For large inputs the pair saturates: with square-law devices, all of ISS flows through one side once |vid| exceeds √2·Vov, where Vov is the overdrive at the balanced point. This sets the linear input range.

5.2 Common-mode gain and CMRR

A common-mode input moves both gates together. If the tail were an ideal current source, the total current could not change, so neither drain current would change and the common-mode gain would be zero. A real tail has a finite output resistance RSS, and some current change gets through. Measured at one output:

Acm ≈ −RD / (1/gm + 2·RSS)  ≈  −RD / (2·RSS)          (5.2)

The figure of merit is the common-mode rejection ratio (CMRR), the ratio of the wanted gain to the unwanted gain. For a single-ended output, where the differential gain is gm·RD/2, this gives approximately

CMRR = |Adm / Acm|  ≈  gm · RSS          (5.3)

A cascoded tail raises RSS and therefore CMRR. With a fully differential output and a perfectly symmetric circuit, the common-mode change would appear equally on both outputs and cancel. In practice, the mismatch described in lesson 6 converts some common-mode signal into a differential one, and that mismatch is what sets the real CMRR.

5.3 The five-transistor OTA

Replacing the resistive loads with a PMOS current mirror gives the circuit in Figure 5.1, the five-transistor OTA. M1 and M2 form the pair, M5 provides the tail current, and M3 and M4 form a mirror that copies the current of M1 to the output branch.

When vin+ rises, M1 carries more current, the mirror pushes that extra current into the output through M4, and at the same time M2 carries less current and pulls less out of it. The two effects add, so the full differential transconductance reaches the output, and

Av = gm1 · (ro2 ∥ ro4)          (5.4)

This is the active-load gain of lesson 3, but now the output DC level is well defined: in a balanced pair, the mirror and the pair agree on the current, and in a feedback loop the output settles where the inputs balance. Two other properties come directly from the circuit. The largest current the output can deliver to a load capacitance CL is ISS, so the slew rate is ISS/CL. And the input common-mode range is bounded by keeping M5 and the input pair in saturation at the bottom and the mirror in saturation at the top.

5.4 The two-stage op-amp

A single stage gives a gain of about half the intrinsic gain, often only 20 to 30 dB in modern processes (lesson 2). An op-amp used in a precise feedback loop usually needs 60 dB or more. The classic solution is to follow the OTA with a second, common-source gain stage: a PMOS M6 driven by the OTA output, with an NMOS current source M7 as its load. The total gain is the product

A0 = gm1·(ro2 ∥ ro4) · gm6·(ro6 ∥ ro7)          (5.5)

Assuming each stage gives 30 dB, the total is 60 dB, about a factor of 1000. The second stage also provides a larger output swing than a cascoded single stage, because it has only two transistors between the rails.

The cost is a second high-impedance node, and with it a second pole. Each high-resistance node forms a pole with the capacitance it sees, and two poles of similar frequency in a feedback loop produce ringing or oscillation. The op-amp therefore needs compensation.

5.5 Miller compensation and gain-bandwidth

The standard technique is to place a capacitor Cc across the second stage, from its output back to its input. Because the second stage has a gain of −A2, the capacitance seen at the first-stage output is multiplied by roughly (1 + A2) – the Miller effect. This deliberately lowers the first pole to a very low frequency, and it also pushes the second pole to a higher frequency, an effect called pole splitting. With R1 and R2 the output resistances of the two stages:

p1  ≈ 1 / (R1 · gm6 · R2 · Cc)       dominant pole        (5.6)
GBW ≈ gm1 / Cc                       unity-gain frequency (5.7)
p2  ≈ gm6 / CL                       non-dominant pole    (5.8)
z   ≈ gm6 / Cc                       right-half-plane zero (5.9)

All values are in rad/s; divide by 2π for hertz. Equation (5.7) is the most useful result of this lesson. The gain-bandwidth product depends only on the input transconductance and the compensation capacitor, not on the gain of either stage. Equation (5.8) assumes CL and Cc are much larger than the internal capacitance at the first-stage output, which is usually true.

The zero in (5.9) is a side effect of Cc feeding signal forward around M6. It lies in the right half-plane, so it adds phase lag while flattening the magnitude – the worst combination. A common fix is a resistor Rz in series with Cc. At Rz = 1/gm6 the zero moves to infinity, and a larger Rz moves it into the left half-plane, where it helps.

5.6 Phase margin and the Bode plot

In a feedback loop, the danger point is the frequency where the loop gain falls to one. If the phase there has reached −180°, the feedback becomes positive and the loop oscillates. The phase margin (PM) is the distance from −180° at that frequency. For a unity-gain buffer, the loop gain equals the op-amp gain, so we can read PM directly from the op-amp's Bode plot in Figure 5.2.

With one dominant pole, the phase at GBW is about −90°. Each pole and right-half-plane zero above GBW adds more lag, so

PM ≈ 90° − arctan(GBW / p2) − arctan(GBW / z)          (5.10)

A phase margin of about 60° is a common target, because it gives a fast step response with little overshoot. Lower margins ring; higher margins are stable but cost bandwidth or power.

5.7 Interview questions

What is CMRR and what limits it? The ratio of differential gain to common-mode gain. In a differential pair it is limited by the finite output resistance of the tail source and, in practice, by device mismatch.

What is the gain of a five-transistor OTA? Av = gm1(ro2 ∥ ro4), the input transconductance times the output resistance at the output node.

Why does a two-stage op-amp need compensation? Each stage has a high-impedance node that forms a pole. Two poles below the unity-gain frequency would drive the phase toward −180° and the loop would oscillate. Miller compensation splits the poles apart.

What sets the gain-bandwidth of a Miller-compensated op-amp? GBW ≈ gm1/Cc, independent of the stage gains.

What is phase margin and what is a typical target? 180° plus the phase of the loop gain at the unity-gain frequency. About 60° is a common target for a well-damped response.