Integrating Analog into a Digital SoC

The previous nine lessons described analog circuits from the inside. This lesson takes the PD engineer's view: an analog block arrives as a finished, signed-off hard macro, and it has to be placed, powered, connected and verified inside a digital SoC without losing the performance its designers worked for. Most integration problems are not circuit problems at all – they are missing views, wrong assumptions about supplies, or a digital net routed where it should not be.

We will look at the views a macro carries, the keep-out and power rules around it, how analog nets are routed, how the whole chip is verified with analog blocks inside, and finally a checklist for the handoff between the AMS and PD teams.

Reading time: about 9 minutes.

10.1 Analog blocks as hard macros

A PLL, ADC or LDO is never re-synthesized or re-placed by the digital flow. Its layout is fixed, and PD sees it through a set of views, each serving a different tool. Table 10.1 lists them.

The LEF is the view the router actually sees, so its quality matters. A simplified example is shown below. The obstruction on lower metals tells the router it may not use those layers anywhere over the macro.

MACRO pll_core
  CLASS BLOCK ;
  SIZE 400 BY 300 ;
  PIN CLKOUT
    DIRECTION OUTPUT ;
    USE CLOCK ;
    PORT
      LAYER M5 ;
        RECT 398.0 150.0 400.0 151.0 ;
    END
  END CLKOUT
  OBS
    LAYER M1 ;
      RECT 0 0 400 300 ;
    LAYER M2 ;
      RECT 0 0 400 300 ;
  END
END pll_core

Thus, if the AMS team wants no routing over the VCO on M3 and M4 as well, that obstruction must be in the LEF, or the router will use those layers freely. It is better to confirm the obstruction layers in a review than to discover a coupling problem in silicon.

10.2 Keep-out and guard

Figure 10.1 shows a PLL macro on a floorplan. Around it the PD engineer typically adds a placement halo – a margin in which no standard cells are placed – and routing blockages on layers where digital nets should not pass.

In Cadence Innovus, for example, a placement halo and a routing blockage can be created with commands such as the following. Exact options differ between versions and between the legacy and Stylus command interfaces, so the tool's own help should be checked.

# legacy Innovus: 10 um halo on all four sides of the PLL instance
addHaloToBlock 10 10 10 10 u_pll

# legacy Innovus: block lower metals over a sensitive region
createRouteBlk -box {200 300 480 510} -layer {M1 M2 M3 M4}

The size of the halo and the blocked layers are not PD choices alone. They come from the AMS team, who know which parts of the macro are sensitive and which aggressors matter. The macro itself normally carries its own guard rings (lesson 6) inside its boundary.

10.3 Power domains and level shifters

Analog blocks rarely run on the core supply. A PLL or ADC might use a 1.8 V analog supply, fed from its own pads or its own LDO, while the core runs below 1 V. This creates three integration requirements:

1. Separate supply nets. The analog supply and ground (often named AVDD and AVSS) are routed separately from the core grid, from their pads or regulator to the macro pins. Merging them with the digital grid would couple digital switching noise straight into the analog circuit.
2. Level shifters. Every digital control signal crossing from the core voltage into the analog domain, and every output crossing back, needs a level shifter unless the macro already contains one.
3. Isolation. If the analog domain can be powered down while the core stays on, its outputs must be clamped to a known value by isolation cells so the core does not see floating inputs.

These intentions are captured in UPF (Unified Power Format). A minimal sketch for an ADC domain might read:

create_power_domain PD_ANA -elements {u_adc}
create_supply_net   AVDD   -domain PD_ANA
set_level_shifter ls_to_ana -domain PD_ANA \
    -applies_to inputs -rule low_to_high -location parent

It is advisable to agree early who owns the level shifters – the macro or the surrounding logic – because a duplicated or missing shifter is a common and costly late finding. The same agreement should cover the power-up sequence the analog block expects.

10.4 Routing analog signals

Some nets on an SoC carry analog values outside the macro: an ADC input from a pad, a reference voltage distributed from a bandgap, a PLL reference clock. These need routing rules the digital flow does not apply by default:

• Shielding – grounded wires run beside the net on both sides, and sometimes a grounded plane below. In Innovus legacy mode, a shield net can be assigned with a net attribute such as setAttribute -net vref_adc -shield_net VSS.
• Spacing and width – a non-default rule (NDR) with extra spacing reduces coupling, and extra width reduces resistance for a reference that carries current.
• Differential pairs – routed together, with equal length and identical surroundings, so that coupled noise appears as common mode and is rejected (lesson 5).
• Avoiding aggressors – no long parallel runs next to clocks or wide buses, and crossings at right angles where unavoidable.

Thus, the most sensitive analog nets are often routed first, by hand or with tight constraints, and then fixed, so that later automatic routing and ECOs cannot disturb them.

10.5 AMS verification

Digital simulation cannot simulate a transistor-level PLL, and a transistor-level simulation of the whole chip would take far too long. Mixed-signal verification bridges the two with models at several levels of detail:

• Verilog-AMS – a language that describes analog behavior with continuous-time equations, solved by an analog engine alongside the digital simulator.
• Real-number modeling (RNM) – analog values carried as real numbers in an event-driven digital simulator, using wreal in Verilog-AMS or real variables and user-defined nettypes in SystemVerilog. It runs at nearly digital speed.
• Co-simulation – a digital simulator coupled to a SPICE-level engine, for example Cadence Xcelium with Spectre, so selected blocks run at transistor level.

Let us consider a simple real-number model of an 8-bit ADC:

module adc8_rnm #(parameter real VREF = 1.0) (
  input  real        vin,
  input  logic       clk,
  output logic [7:0] code
);
  always @(posedge clk) begin
    if (vin <= 0.0)       code <= 8'd0;
    else if (vin >= VREF) code <= 8'd255;
    else                  code <= $rtoi(vin / VREF * 256.0);
  end
endmodule

A model like this cannot check noise or linearity. It can check what most chip-level failures actually come from: wrong connections, inverted enables, missing clocks, incorrect power-up order, and digital calibration loops that do not converge. It is recommended to validate each model against the transistor-level circuit, because an inaccurate model gives false confidence.

10.6 The AMS–PD handoff

Figure 10.2 shows what passes between the two teams. Information flows both ways: PD needs views and rules, and the AMS team needs to know where the block will sit and what environment it will see.

Table 10.2 turns this into a checklist. It is prudent to review it at the first floorplan and again whenever the macro is re-released.

10.7 Interview questions

Which views does an analog hard macro need for PD, and what is each used for? GDS for chip assembly and sign-off, LEF for placement and routing, LIB for STA and power, a Verilog stub for connectivity, CDL for LVS and a behavioral model for AMS verification.

Why are analog supplies kept separate from the core power grid? Digital switching currents create noise on the core grid, and an analog block such as a PLL or ADC converts supply noise directly into jitter or conversion error.

When are level shifters needed around an analog macro? When control or data signals cross between the core voltage and the analog supply voltage. Isolation is also needed if the analog domain can be switched off while the core is on.

What is real-number modeling and why is it used? It represents analog values as real numbers in an event-driven simulator, allowing chip-level mixed-signal checks at nearly digital speed.

How would you route a reference voltage from a bandgap to an ADC across the chip? As a pre-routed, shielded net with ground wires on both sides, extra spacing, away from clocks and buses, and fixed so later routing and ECOs do not disturb it.