The Analog Design Flow

A digital block moves from RTL to GDS through a largely automated chain: synthesis, placement, clock tree synthesis, routing and sign-off. An analog block follows a different flow, built around a schematic, a simulator and a hand-drawn layout. The steps are fewer, but each one is iterated many times, and the designer, not a tool, decides when the circuit is good enough.

This lesson walks through that flow from specification to post-layout verification. The tools named are those most commonly found in industry, chiefly the Cadence Virtuoso environment and the Spectre simulator; other vendors offer equivalent steps under different names.

Reading time: about 7 minutes.

9.1 The flow at a glance

Let us consider Figure 9.1. The flow runs down the left column, from specification to layout, and up the right column through physical verification and post-layout simulation. The dashed arrows are as important as the solid ones: an analog block typically passes around these loops several times before it is released.

9.2 Specification and schematic capture

The flow starts with a specification – gain, bandwidth, noise, offset, power, area, supply range, temperature range and load conditions – usually negotiated with the system architects. It is better to agree the specification in numbers before drawing anything, because every later decision, from device lengths to the number of corners, is checked against it.

The designer then draws the circuit in a schematic editor, typically the Virtuoso Schematic Editor. Devices are instantiated from the foundry's process design kit (PDK), which provides parameterized transistors, resistors, capacitors and their simulation models. A second schematic, the testbench, surrounds the circuit with ideal sources, loads and stimulus. Keeping the circuit and its testbenches separate lets the same block be tested in many conditions without editing it.

9.3 Simulation types

Unlike STA, analog verification is done by simulation, and each analysis answers a different question. Table 9.1 lists the ones used most often.

In Spectre, each analysis is a named statement in the netlist. A schematic environment such as ADE generates these lines, but it helps to recognize them. The snippet below is illustrative; the model name nch stands for whatever the PDK provides.

simulator lang=spectre
// instance: name (drain gate source bulk) model parameters
M1 (out in 0 0) nch w=2u l=180n

// analyses
dcop   dc
ac1    ac    start=1 stop=10G dec=20
tran1  tran  stop=100n
noise1 (out 0) noise start=1 stop=1G dec=10 iprobe=VIN

Here dcop computes the operating point, ac1 sweeps from 1 Hz to 10 GHz with 20 points per decade, tran1 runs for 100 ns, and noise1 computes the noise at node out, referred to the input source VIN. Exact options vary between simulator versions, so it is prudent to check the simulator's own reference manual before relying on one.

9.4 PVT corners and Monte Carlo

A circuit that works at one temperature, one supply and typical devices has not yet been proved. Two complementary methods cover variation.

9.4.1 PVT corners

PVT stands for process, voltage and temperature. The foundry supplies process corners such as TT (typical NMOS, typical PMOS), FF, SS, and the skewed corners FS and SF, where the first letter refers to the NMOS. The supply is typically varied by a stated percentage around nominal, and temperature across the product range.

9.4.2 Monte Carlo

Corners capture global shifts that affect every device on a die together. They do not capture the random device-to-device mismatch of lesson 6. A Monte Carlo analysis draws random values for the statistical model parameters, runs the simulation many times, and reports the distribution of each result. In Spectre, a Monte Carlo analysis wraps the analyses to be repeated:

mc1 montecarlo numruns=200 seed=1 variations=mismatch {
    dcop1 dc
}

The variations parameter selects process variation, mismatch, or both. From the results, the designer reads the mean and standard deviation of quantities such as offset, and checks that the specification holds at the required number of standard deviations – often three sigma or more. Thus, corners answer "does it work at the edges of the process?" and Monte Carlo answers "what fraction of parts will work?".

9.5 Layout

Once the schematic meets specification across corners and Monte Carlo, the layout engineer draws it, typically in Virtuoso Layout using the PDK's parameterized cells (PCells). Analog layout is placed and wired mostly by hand, applying the matching techniques of lesson 6 – common centroid, interdigitation, dummies, guard rings – and paying attention to current density in wide wires and to symmetry in differential paths. Layout-aware tools can generate devices from the schematic and keep the two connected, but the placement decisions remain the engineer's.

9.6 DRC and LVS

Two physical verification checks follow:

• DRC (design rule check) – verifies that every shape obeys the foundry's manufacturing rules: widths, spacings, enclosures, densities and many more.
• LVS (layout versus schematic) – extracts the devices and connections from the layout and compares them with the schematic netlist, including device sizes.

Common tools include Siemens Calibre, Cadence Pegasus and Synopsys IC Validator, run with the foundry's rule decks. These are the same tools and decks that PD uses for full-chip sign-off, which is one reason the analog macro must be clean on its own before integration.

9.7 Parasitic extraction and post-layout simulation

The layout adds resistance and capacitance that the schematic never had: wire resistance in source connections, coupling capacitance between adjacent signals, extra junction capacitance from diffusion sharing. Parasitic extraction computes these from the layout. Typical tools include Cadence Quantus, Siemens Calibre xACT and Synopsys StarRC, producing an extracted view or a netlist such as DSPF (detailed standard parasitic format).

The designer then re-runs the critical tests on the extracted netlist. Usually, bandwidth falls, phase margin shrinks and noise coupling appears where the schematic was clean. If a result fails, the designer returns to sizing or the layout engineer reshapes the wiring – the dashed loop in Figure 9.1. Post-layout results, not schematic results, are what the block is signed off against.

9.8 What comes out of the flow

When the block is signed off, the team produces the views other teams need: the GDS layout, an abstract LEF view for placement and routing, a timing and power model for its digital pins, a netlist for full-chip LVS, and a behavioral model for mixed-signal verification. Lesson 10 describes each of these and how PD uses them.

9.9 Interview questions

What is the difference between AC and transient analysis? AC analysis linearizes the circuit at its operating point and computes the small-signal frequency response. Transient analysis simulates the full non-linear circuit over time.

Why are both PVT corners and Monte Carlo needed? Corners cover global process, supply and temperature shifts that affect all devices together. Monte Carlo covers random local mismatch between devices, which corners do not model.

What do DRC and LVS check? DRC checks the layout against manufacturing rules. LVS checks that the devices and connectivity extracted from the layout match the schematic.

Why is post-layout simulation necessary? Layout adds parasitic resistance and capacitance that reduce bandwidth and phase margin and introduce coupling. Only post-layout results show the circuit as built.