PLLs and Clock Generation

Every synchronous digital block needs a clock, and the clock frequencies an SoC uses – often in the gigahertz range – cannot come directly from off-chip. A crystal oscillator gives a very clean but low-frequency reference, typically in the tens of megahertz. The phase-locked loop (PLL) multiplies that reference up to the required frequency while keeping as much of its cleanliness as possible.

This lesson describes the five blocks of a charge-pump PLL, how the loop achieves lock, the difference between jitter and phase noise, and why the PLL is one of the most demanding hard macros a PD engineer integrates.

Reading time: about 9 minutes.

8.1 What a PLL does

A PLL is a feedback system that forces the phase of an oscillator to track the phase of a reference. If the oscillator output is divided by N before it is compared with the reference, the loop can only be satisfied when the divided output runs at exactly the reference frequency. Therefore

fout = N · fref          (8.1)

Let us consider a 25 MHz crystal reference and a divider ratio of 80. The PLL output is then 2 GHz. Changing N changes the output frequency, which is how one PLL can serve several operating modes. Dividers that switch between N and N+1 under the control of a sigma-delta modulator give fractional ratios – a fractional-N PLL – but the principle is the same.

8.2 The blocks of a charge-pump PLL

Figure 8.1 shows the loop. Each block has a single job.

8.2.1 Phase-frequency detector

The phase-frequency detector (PFD) compares the rising edges of fref and fdiv. If the reference edge arrives first, it raises an UP output; if the divided edge arrives first, it raises DN. When both edges have arrived, both outputs reset. The width of the pulse is therefore proportional to the phase error. Unlike a simple XOR phase detector, the PFD also responds correctly to a frequency difference, which lets the loop acquire lock from far away. A short reset delay is usually added so that both outputs always produce a minimum pulse, avoiding a dead zone where very small phase errors produce no correction.

8.2.2 Charge pump

The charge pump converts the UP and DN pulses into current: it sources a current Icp into the loop filter while UP is high and sinks Icp while DN is high. Averaged over a reference period, the delivered current is proportional to the phase error, Icp·Δφ/(2π). Mismatch between the up and down currents shows up as a static phase offset and as spurs at the reference frequency, so the two current sources are matched with the techniques of lesson 4 and lesson 6.

8.2.3 Loop filter

The simplest common loop filter is a resistor R in series with a capacitor C1, with a small capacitor C2 in parallel. C1 integrates the charge-pump current, which means that in lock the phase error goes to zero – a so-called type-II loop. R introduces a zero that provides phase margin, exactly the stability concern of lesson 5. C2 smooths the ripple that each correction pulse leaves on the control voltage. The capacitors can be large, and the loop filter is often a significant part of the PLL area.

8.2.4 Voltage-controlled oscillator

The VCO produces a frequency that rises with the control voltage, approximately fout = f0 + KVCO·Vctrl, where KVCO is the tuning gain in Hz/V. Two families are common:

• Ring oscillators – an odd number of inverting stages in a loop. Compact and widely tunable, but with relatively high phase noise and strong sensitivity to supply noise.
• LC oscillators – an inductor and a varactor tank. Much lower phase noise, but the inductor occupies a large area and the tuning range is narrower. SerDes and RF PLLs commonly use them.

8.2.5 Divider

The divider is digital logic, but its first stages run at the full VCO frequency, so they are usually custom high-speed circuits rather than standard cells.

8.3 Lock and loop bandwidth

At start-up, the PFD sees a frequency difference and drives the control voltage steadily in one direction – frequency acquisition. As the frequencies converge, the loop settles the remaining phase error – phase acquisition. A lock detector watches the UP and DN pulses, and once they stay narrow for a number of reference cycles, it signals the digital side that the clock is usable. Typically, the clock is gated off from the core until lock is declared.

The loop bandwidth describes how fast the loop corrects errors. Because the PFD only acts once per reference period, the loop bandwidth is usually kept well below the reference frequency; a common rule of thumb is about one tenth of fref or less. A wider loop locks faster and suppresses VCO noise over a wider range; a narrower loop filters more reference and charge-pump noise. Choosing it is the central trade-off of PLL design, as the next section shows.

8.4 Jitter and phase noise

An ideal clock has its edges at exact multiples of the period. A real clock's edges wander slightly. The same imperfection has two descriptions:

• Jitter is the time-domain view – the deviation of edge times from their ideal positions. Period jitter is the variation of single periods, cycle-to-cycle jitter the difference between adjacent periods, and long-term or accumulated jitter the deviation over many cycles. Jitter is usually quoted as rms, sometimes as peak-to-peak for a stated number of cycles or error rate.
• Phase noise is the frequency-domain view – the noise power in the sidebands around the carrier, at an offset Δf, relative to the carrier power and in a 1 Hz bandwidth. It is written L(Δf) and expressed in dBc/Hz.

Figure 8.2 shows the typical shape. Inside the loop bandwidth, the loop suppresses VCO noise, and the output follows the noise of the reference, PFD, charge pump and divider, multiplied by N. Outside it, the loop cannot react, and the output follows the free-running VCO.

The two descriptions are connected. Integrating the phase noise over the offset band of interest gives the rms phase error σφ in radians, and

σt = σφ / (2π · f0)          (8.2)

For digital timing, the PLL jitter specification feeds directly into the clock uncertainty that STA applies. A designer who uses an optimistic jitter number in set_clock_uncertainty hides a real loss of timing margin.

8.5 Why the PLL is a hard macro to PD

The PLL is delivered as a hard macro, and it is among the most sensitive blocks on the die. The PD engineer should expect, and enforce, the following:

1. Clean supply. The VCO converts supply noise directly into phase noise, especially a ring oscillator. The PLL typically has its own analog supply pins, often fed from a dedicated LDO (lesson 4), and these must not be merged with the core grid.
2. Keep-out and no routing over. Digital nets routed over the VCO or loop filter couple switching noise into the most sensitive nodes. The macro abstract usually carries routing blockages, and a placement halo keeps aggressive logic away.
3. Placement. The PLL is placed close to its reference clock pad, so the reference path is short and quiet, and in a position from which its output can reach the clock tree root without crossing noisy regions.
4. Shielded clock nets. The reference input and the clock output are typically shielded and routed with non-default rules.
5. Timing definition. The PLL output is a clock source. In SDC, it is commonly defined either as a generated clock related to the reference or as a new clock on the PLL output pin, depending on the flow:

# Option 1: generated clock related to the reference (25 MHz x 80 = 2 GHz)
create_generated_clock -name clk_pll -source [get_ports ref_clk] \
    -multiply_by 80 [get_pins u_pll/CLKOUT]

# Option 2: a new clock on the PLL output pin
create_clock -name clk_pll -period 0.5 [get_pins u_pll/CLKOUT]

The pin and instance names here are illustrative; the macro's own documentation gives the real ones. Which option a team uses depends on whether it needs STA to relate the reference and the PLL clock – for example, for paths between them. Lesson 10 collects these and the other integration requirements into a single handoff checklist.

8.6 Interview questions

Name the blocks of a charge-pump PLL and their roles. The PFD compares reference and divided edges, the charge pump converts the phase error into current, the loop filter turns current into a control voltage and stabilizes the loop, the VCO generates the output, and the divider scales it back to the reference frequency.

Why use a PFD rather than an XOR phase detector? A PFD detects frequency as well as phase error, so the loop can acquire lock over a wide range, and it gives zero static phase error in a type-II loop.

What is the difference between jitter and phase noise? Jitter is the time-domain deviation of clock edges; phase noise is the frequency-domain sideband power. Integrated phase noise converts to rms jitter through σt = σφ/(2πf0).

How does loop bandwidth affect PLL noise? A wider loop suppresses VCO noise over more of the spectrum but passes more reference and charge-pump noise; a narrower loop does the opposite.

What does a PD engineer need to protect around a PLL? Its dedicated supply, a keep-out region with no digital routing over the VCO and loop filter, short shielded reference and output clock routes, and correct clock definitions in SDC.