Analog & Mixed-Signal · lesson 2

The MOSFET as an Analog Device

Regions of operation, the square law, transconductance, output resistance, intrinsic gain and gm/ID sizing, with the small-signal model.

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In digital design, a MOSFET is treated as a switch: on or off, with a resistance and a capacitance that set the delay. In analog design, the same device is used in between those two states, where a small change in gate voltage produces a proportional change in drain current. This lesson describes the MOSFET from that point of view and introduces the four quantities every later lesson relies on: overdrive voltage, transconductance, output resistance and intrinsic gain.

As mentioned in lesson 1, we keep the equations at the textbook level. They describe long-channel behavior well and short-channel behavior only approximately, and we will say where that difference matters.

Reading time: about 8 minutes.

2.1 Regions of operation

Let us consider an NMOS transistor with its source grounded, a gate-source voltage VGS and a drain-source voltage VDS. The threshold voltage VTH is the gate voltage at which a conducting channel forms. The device then operates in one of three regions:

  1. Cut-off – VGS < VTH. No channel forms, and the drain current is ideally zero. In practice a small subthreshold current flows, which section 2.6 returns to.
  2. Triode (linear) – VGS > VTH and VDS < VGS − VTH. The channel extends from source to drain, and the device behaves like a voltage-controlled resistor. This is the region a digital switch uses when it is fully on.
  3. Saturation – VGS > VTH and VDS ≥ VGS − VTH. The channel pinches off near the drain, and the current depends mainly on VGS, only weakly on VDS. This is the region almost every analog amplifier and current source uses.

The difference VGS − VTH appears so often that it gets its own name, the overdrive voltage, written Vov. It is also the minimum VDS that keeps the device in saturation, sometimes called VDS,sat. Thus, a transistor biased with an overdrive of 0.2 V needs at least 0.2 V across it, and every device stacked between the supply rails consumes at least that much headroom.

2.2 The square law

For a long-channel device in triode, the drain current is

ID = μn·Cox·(W/L)·[ (VGS − VTH)·VDS − VDS²/2 ]          (2.1)

and in saturation it becomes

ID = ½·μn·Cox·(W/L)·(VGS − VTH)²·(1 + λ·VDS)             (2.2)

Here μn is the electron mobility, Cox the gate-oxide capacitance per unit area, W and L the channel width and length, and λ the channel-length modulation coefficient, described in section 2.4. For a PMOS device the same equations apply with the signs of the voltages reversed and the hole mobility μp, which is typically two to four times lower than μn – so a PMOS needs a wider channel for the same current.

Figure 2.1 plots equation (2.1) and (2.2) for three values of overdrive. The dashed curve marks VDS = Vov, the boundary between the two regions.

ID VDS Vov = 0.4 V Vov = 0.3 V Vov = 0.2 V VDS = VGS − VTH Triode Saturation slope = 1/ro
Figure 2.1 Drain current against drain-source voltage for three overdrive voltages. Left of the dashed boundary the device is a voltage-controlled resistor; right of it the current is set mainly by the overdrive. The small upward slope in saturation is channel-length modulation, and its inverse is the output resistance ro.

Notice that the saturation current rises with the square of the overdrive – doubling Vov from 0.2 V to 0.4 V gives four times the current. Modern short-channel devices deviate from this, with the current growing closer to linearly at large overdrive because of velocity saturation. The square law remains the standard first-pass model, and designers then refine the sizing in simulation with the real device models.

2.3 Transconductance

An amplifier uses a small change in gate voltage to produce a change in drain current. The ratio of the two is the transconductance:

gm = ∂ID / ∂VGS
   = μn·Cox·(W/L)·Vov                 (2.3a)
   = √( 2·μn·Cox·(W/L)·ID )           (2.3b)
   = 2·ID / Vov                       (2.3c)

All three forms are the same quantity, but each answers a different design question. Form (2.3b) says that at a fixed W/L, gm grows only with the square root of current. Form (2.3c) says that at a fixed overdrive, gm grows linearly with current. Lesson 1 used form (2.3c) when it concluded that four times the gm costs four times the current.

The source terminal also has an effect. When the source is not at the body potential, the body acts as a second gate, adding a transconductance gmb, usually a fraction of gm. We will include gmb only where it changes a result noticeably, such as the source follower in lesson 3.

2.4 Output resistance and channel-length modulation

In saturation, increasing VDS moves the pinch-off point slightly toward the source, shortening the effective channel and increasing the current. This is channel-length modulation, modelled by the factor (1 + λVDS) in equation (2.2). Its small-signal effect is a finite output resistance:

ro = ∂VDS / ∂ID ≈ 1 / (λ·ID)          (2.4)

Since λ is roughly inversely proportional to the channel length, a longer device has a higher ro at the same current. This is the main reason analog designers often draw transistors longer than the minimum length that digital cells use.

2.5 Intrinsic gain

The product gm·ro is the largest voltage gain a single transistor can provide, so it is called the intrinsic gain. Using (2.3c) and (2.4):

gm·ro = (2·ID / Vov) · (1 / (λ·ID)) = 2 / (λ·Vov)     (2.5)
Worked example

Let us size an NMOS device for a drain current of 100 µA. Assumptions are stated as they are made.

  • Assuming Vov = 0.2 V: gm = 2 × 100 µA / 0.2 V = 1 mS.
  • Assuming λ = 0.1 V⁻¹ at the chosen length: ro = 1 / (0.1 × 100 µA) = 100 kΩ.
  • Intrinsic gain: gm·ro = 1 mS × 100 kΩ = 100, which is 40 dB. Equation (2.5) agrees: 2 / (0.1 × 0.2) = 100.
  • Assuming μn·Cox = 300 µA/V²: W/L = 2·ID / (μn·Cox·Vov²) = 200 µA / (300 µA/V² × 0.04 V²) ≈ 16.7.

If L is doubled and W doubled with it, W/L and gm stay the same, λ roughly halves, and the intrinsic gain roughly doubles to 200. The price is four times the gate area, and therefore more gate capacitance and a slower device.

In deep-submicron processes, intrinsic gain at minimum length is often only in the range of ten to a few tens, much lower than in older nodes. That is why later lessons rely on cascodes (lesson 3) and multi-stage amplifiers (lesson 5) to recover gain.

2.6 The small-signal model

For an amplifier, the designer first finds the DC bias point, then asks how small changes around it behave. The device is replaced by the linear small-signal model of Figure 2.2: a voltage-controlled current source gm·vgs from drain to source, in parallel with ro, and a gate-source capacitance Cgs. Lowercase symbols such as vgs denote small changes around the bias point.

G D S Cgs + − vgs gm·vgs ro id = gm·vgs + vds / ro
Figure 2.2 The low-frequency small-signal model of a MOSFET in saturation, with Cgs added. The gate draws no DC current; the drain current is a controlled source gm·vgs plus the current through ro. Every amplifier in lesson 3 is analyzed by drawing this model in place of each transistor.

A fuller model adds gmb·vbs, the gate-drain capacitance Cgd and the junction capacitances, but the simple version is enough to derive the gain of every circuit in lessons 3 to 5.

2.7 gm/ID as a design variable

The square law becomes inaccurate at both ends of the bias range – at large overdrive because of velocity saturation, and at small overdrive because the device enters moderate and weak inversion, where the current depends exponentially on VGS. Many designers therefore size transistors using the ratio gm/ID instead of Vov.

The ratio gm/ID answers one question directly: how much transconductance do we get per unit of current? In strong inversion, (2.3c) gives gm/ID = 2/Vov. In weak inversion, gm/ID approaches its maximum of 1/(n·UT), where UT = kT/q ≈ 26 mV at room temperature and n is the subthreshold slope factor, typically between about 1.2 and 1.5. Table 2.1 summarizes the regions.

Table 2.1 Approximate gm/ID by inversion level (typical values, process dependent)
RegionApproximate gm/IDStrengthCost
Strong inversionabout 5 to 10 V⁻¹fast, compact device, good matching of currentmore current per unit gm
Moderate inversionabout 10 to 20 V⁻¹balanced power and speedsquare law is inaccurate here
Weak inversionabout 20 to 30 V⁻¹most gm per unit currentlarge, slow device

The method is to simulate the actual device once, store gm/ID, current density ID/W and intrinsic gain against gm/ID, and then size every transistor from those tables. Since the tables come from the real models, they include the short-channel effects that the square law misses. Thus, gm/ID replaces a formula with a measured curve while keeping the hand-analysis intuition.

2.8 Interview questions

What are the conditions for an NMOS transistor to be in saturation? VGS > VTH and VDS ≥ VGS − VTH, that is, the drain-source voltage must be at least the overdrive voltage.

Write gm in three forms and explain when each is useful. gm = μnCox(W/L)Vov = √(2μnCox(W/L)ID) = 2ID/Vov. The second form shows the effect of current at fixed size, the third the effect of current at fixed overdrive.

What is intrinsic gain and how can it be increased? It is gm·ro = 2/(λVov), the maximum gain of a single transistor. It increases with longer channels (smaller λ) and lower overdrive, at the cost of area and speed.

Why do analog designers use gm/ID instead of the square law? Because short-channel and moderate-inversion behavior is poorly described by the square law, while gm/ID tables taken from simulation capture the real device across all regions.

Key takeaways

  • Analog circuits mostly bias transistors in saturation, which requires VDS ≥ Vov.
  • Transconductance gm = 2ID/Vov converts a gate voltage change into a drain current change.
  • Channel-length modulation gives a finite output resistance ro ≈ 1/(λID), larger for longer devices.
  • Intrinsic gain gm·ro = 2/(λVov) is the gain limit of one device, and it is low in modern nodes.
  • gm/ID is a practical sizing variable that trades power efficiency against speed and area.