Characterization and Liberty

A static timing analysis (STA) tool does not simulate transistors. When it times a path through a NAND2 or through a memory macro, it looks up numbers in a model that someone prepared in advance. Preparing those numbers is called characterization, and the model format used almost everywhere is Liberty, usually seen as a .lib file.

This lesson explains what characterization measures, how a non-linear delay model (NLDM) table works, how setup, hold and power are represented, and what the timing arcs of a memory macro look like. It uses the standard cells of lesson 3 and the memory timing parameters of lesson 6. All times are in nanoseconds and all capacitances in picofarads, unless otherwise mentioned.

Reading time: about 9 minutes.

9.1 What characterization is

For each cell, characterization runs circuit simulation (SPICE) on the cell's netlist, including its extracted parasitics, and measures how the cell behaves under a range of conditions. A timing arc is a cause-and-effect pair, such as "a rising edge on input A causes a falling edge on output Y". For each arc, the simulation is repeated over a grid of input transition times and output loads, and the results are stored as tables.

The process is repeated for every corner: a combination of process (slow, typical, fast devices), voltage and temperature. A library for one process may therefore consist of many Liberty files, one per corner. Commercial characterization tools, such as Cadence Liberate or Synopsys SiliconSmart, automate the simulation setup and the writing of Liberty. For memory macros, the compiler usually characterizes its leaf cells and critical paths in advance and assembles the model for each configuration, although the method varies by vendor.

Before any table can be filled, the measurement points must be defined. Liberty states them explicitly with attributes such as input_threshold_pct_rise and output_threshold_pct_fall (commonly 50 percent, so delay is measured from 50 percent of the input swing to 50 percent of the output swing) and slew_lower_threshold_pct_rise and slew_upper_threshold_pct_rise (commonly 10 and 90, or 20 and 80 percent, for transition time). The STA tool reads these so that it interprets the numbers the same way they were measured.

9.2 The NLDM table

The delay of a cell depends mainly on two things: how fast its input changes (the input transition, or slew) and how much capacitance its output drives. In the non-linear delay model, each arc stores a two-dimensional table of delay against these two variables, and a second table of output transition. Let us consider Fig. 9.1.

When the actual slew and load fall between the grid points, the STA tool interpolates between the four surrounding entries. When they fall outside the table, the tool must extrapolate, which is much less accurate. Hence, the library team chooses index values that cover the range the cells will see in real designs, and PD engineers set maximum transition and capacitance limits so that cells stay inside their tables.

## Fraction along each axis
t_slew = (0.06  - 0.02 ) / (0.10  - 0.02 ) = 0.50
t_load = (0.010 - 0.005) / (0.020 - 0.005) = 0.333

## Interpolate along load, at each of the two slews
at slew 0.02 : 0.045 + 0.333 x (0.080 - 0.045) = 0.0567
at slew 0.10 : 0.060 + 0.333 x (0.096 - 0.060) = 0.0720

## Interpolate along slew
delay = 0.0567 + 0.50 x (0.0720 - 0.0567)      = 0.064 ns

NLDM models the output as a simple ramp into a lumped capacitance. At advanced nodes, where wire resistance is significant, most flows use current-source models (CCS or ECSM), which store the output current waveform instead. Many libraries also add the Liberty Variation Format (LVF), which stores the standard deviation of delay at each table entry for statistical timing. The table structure, however, is the same idea.

9.3 Setup and hold arcs

For a sequential cell, characterization also measures constraints. The setup time is the latest a data input may change before the clock edge and still be captured correctly; the hold time is how long it must stay stable after the edge. Characterization finds them by moving the data edge closer to the clock edge in simulation until the output fails, or until the clock-to-output delay degrades by a chosen percentage.

Constraints are also stored as tables, but they are indexed by the clock transition and the data transition rather than by load. In Liberty, the arc has timing_type : setup_rising or hold_rising for a rising-edge clock, a related_pin naming the clock, and rise_constraint and fall_constraint tables for rising and falling data.

9.4 Power tables

Power is modelled in two parts. Internal power is the energy consumed inside the cell per transition, including short-circuit current and the charging of internal nodes; it is stored as tables against slew and load, in the same format as delay. Leakage power is the static power when the cell is idle, usually given per input state with a when condition. For a memory, the most useful power figures are the energy per read access and per write access, which are typically attached to the clock pin with when conditions on the enable pins, plus leakage in each low-power mode.

9.5 Timing arcs of a memory macro

From the outside, a synchronous SRAM behaves like a large, slow register: all inputs are captured on the clock edge, and outputs change some time after it. Let us consider Fig. 9.2.

A memory Liberty model therefore contains, at minimum, the following arcs.

• CLK to Q – a delay arc with timing_type : rising_edge, indexed by clock slew and output load.
• Setup and hold on the address, data, chip enable, write enable and any write-mask pins, relative to CLK.
• Minimum pulse width for the clock high and low, and often a minimum period.
• Pin capacitances on every input, and power and leakage for each operating mode.

The excerpt below shows the shape of such a model. The values are illustrative and many required details are omitted:

library (sram_2048x64_ss_0p72v_125c) {
  delay_model : table_lookup ;
  time_unit : "1ns" ;
  capacitive_load_unit (1, pf) ;
  lu_table_template (delay_3x3) {
    variable_1 : input_net_transition ;
    variable_2 : total_output_net_capacitance ;
    index_1 ("0.02, 0.10, 0.40") ;
    index_2 ("0.005, 0.020, 0.080") ;
  }
  lu_table_template (constraint_2x2) {
    variable_1 : related_pin_transition ;
    variable_2 : constrained_pin_transition ;
    index_1 ("0.02, 0.40") ;
    index_2 ("0.02, 0.40") ;
  }
  type (bus_a) { base_type : array ; data_type : bit ; bit_width : 11 ; bit_from : 10 ; bit_to : 0 ; }
  type (bus_q) { base_type : array ; data_type : bit ; bit_width : 64 ; bit_from : 63 ; bit_to : 0 ; }
  cell (sram_2048x64) {
    pin (CLK) {
      direction : input ;
      clock : true ;
      capacitance : 0.004 ;
      min_pulse_width_high : 0.20 ;
      min_pulse_width_low : 0.20 ;
    }
    bus (A) {
      bus_type : bus_a ;
      direction : input ;
      capacitance : 0.002 ;
      timing () {
        related_pin : "CLK" ;
        timing_type : setup_rising ;
        rise_constraint (constraint_2x2) { values ("0.12, 0.15", "0.10, 0.13") ; }
        fall_constraint (constraint_2x2) { values ("0.12, 0.15", "0.10, 0.13") ; }
      }
      /* a second timing () group with timing_type : hold_rising follows */
    }
    bus (Q) {
      bus_type : bus_q ;
      direction : output ;
      timing () {
        related_pin : "CLK" ;
        timing_type : rising_edge ;
        cell_rise (delay_3x3) {
          values ("0.48, 0.51, 0.60", "0.50, 0.53, 0.62", "0.55, 0.58, 0.67") ;
        }
        /* rise_transition, cell_fall and fall_transition tables follow */
      }
    }
  }
}

Notice two differences from a flip-flop model. The clock-to-Q delay starts large (about 0.5 ns here) even at the smallest load, because it includes the whole internal access of lesson 6. And the address setup is relatively large, because the address must pass through the predecoder before the internal timing begins. In STA, this appears as a path from a launching flop to the memory address pin that has less of the cycle available than an ordinary flop-to-flop path.

9.6 Corners

A corner is named by its process, voltage and temperature, for example ss_0p72v_125c, tt_0p80v_25c or ff_0p88v_m40c (naming conventions vary). Setup checks are usually signed off at the slow corners and hold checks at the fast ones. At advanced nodes, temperature inversion means the slowest corner may be at low temperature rather than high, so both temperature extremes are often checked at the slow process.

A memory macro must be characterized at every corner the chip is signed off at, and its corner names must match those of the standard-cell libraries so that the STA tool pairs them correctly. If the memory has separate array and periphery supplies, its corners are defined by both voltages. Thus, a missing or mismatched memory corner is one of the more common causes of an incomplete signoff run.

9.7 Interview questions

What are the two indices of an NLDM delay table? The input transition time and the total output load capacitance.

What happens if a cell operates outside its table range? The tool extrapolates, which can be inaccurate. That is one reason for maximum transition and capacitance limits.

How is setup time characterized? By moving the data edge closer to the clock edge in simulation until capture fails, or until clock-to-output delay degrades by a set percentage, across a grid of clock and data slews.

Why is a memory's clock-to-Q delay so much larger than a flip-flop's? It includes the full internal access: decode, wordline rise, bitline development, sensing and output drive.