Memory Test, Repair and Reliability

A memory that cannot be tested cannot be shipped, and a large memory is almost certain to contain some defective cells. For these two reasons, every memory on a chip is surrounded by test and repair logic, and many are protected by error-correcting codes in the field. This lesson closes the path by explaining how memories are tested, what faults the tests look for, how defective cells are replaced, and how memories are protected against soft errors and low-voltage failure.

The lesson draws on the array organization of lesson 5, the eFuses of lesson 7 and the compiler options of lesson 8.

Reading time: about 9 minutes.

10.1 Why memories need their own test

Logic is tested mainly with scan: flip-flops are chained together, patterns are shifted in, and the responses are shifted out. A memory array has no scan chain inside it. It also fails in ways that logic does not. Cells are packed at push-rule density (lesson 4), so a defect may couple two neighbouring cells, slow down a transition, or make a cell lose its data after a while. Testing every one of millions of cells through the chip pins with an external tester would also take too long.

The solution is memory built-in self-test (MBIST): a small controller on the chip that writes and reads the memory with algorithmic patterns at full speed and reports the result. MBIST logic is usually generated and inserted by a dedicated EDA tool from the memory's configuration.

10.2 MBIST architecture

Let us consider Fig. 10.1.

The main parts are:

• Controller – sequences the test algorithm and is usually started and monitored through the chip's test access port.
• Address and data generators – produce ascending and descending address sequences and data patterns, called data backgrounds (all zeros, checkerboard, and so on).
• Input multiplexer – often called a collar or wrapper, it switches the memory inputs between functional logic and the controller. It adds a little delay to the functional path, which the timing of lesson 9 must include.
• Comparator – compares read data with the expected value and records pass, fail and, for repair, the failing address and bit.

10.3 Fault models

A test is designed against a list of fault models – simple, abstract descriptions of how a defect makes a memory misbehave. The most common are:

• Stuck-at fault (SAF) – a cell is always 0 or always 1.
• Transition fault (TF) – a cell cannot make one of the transitions, 0 to 1 or 1 to 0.
• Coupling fault (CF) – an operation on one cell (the aggressor) changes another cell (the victim). An inversion coupling fault flips the victim; an idempotent coupling fault forces it to a fixed value; a state coupling fault forces the victim only while the aggressor holds a certain value.
• Address decoder fault (AF) – an address reaches no cell, the wrong cell, or several cells.
• Data retention fault (DRF) – a cell loses its value after some time, typically from a weak pull-up or excess leakage.

Thus, a good test writes and reads every cell in both states, makes every cell change in both directions, and does so in an order that lets a disturbance in one cell be seen when a neighbour is read later.

10.4 March tests and March C-

A march test is a sequence of march elements. Each element visits every address in a stated order and performs the same short list of operations at each one before moving to the next address. In the usual notation, w0 and w1 mean write 0 or 1, r0 and r1 mean read and expect 0 or 1, and the address order is written as ascending, descending, or either.

The most widely taught algorithm is March C-, which has six elements:

M0: either order    { w0 }
M1: ascending       { r0, w1 }
M2: ascending       { r1, w0 }
M3: descending      { r0, w1 }
M4: descending      { r1, w0 }
M5: either order    { r0 }

Figure 10.2 shows the same elements as a chart.

For a memory of N words, March C- takes 10N operations. It detects all stuck-at, transition and address decoder faults, and the unlinked inversion, idempotent and state coupling faults between any two cells. The ascending and descending passes catch coupling faults whether the victim lies above or below the aggressor.

M0 (any):   w0 at 0,1,2,3         -> cells = 0 0 0 0
M1 (up):    addr 0: r0 ok, w1     -> 1 0 0 0
            addr 1: r0 ok, w1     -> 1 1 0 0
            addr 2: r0 ok, w1     -> 1 1 0 0   (write fails silently)
            addr 3: r0 ok, w1     -> 1 1 0 1
M2 (up):    addr 0: r1 ok, w0
            addr 1: r1 ok, w0
            addr 2: r1 expected, read 0  -> FAIL at address 2

10.5 Redundancy and repair

Because some defects are almost unavoidable in large arrays, compilers can add redundancy: spare rows, spare columns, or both. During wafer test, MBIST finds the failing cells and a repair analysis – on the chip (built-in redundancy analysis) or on the tester – decides which spares replace which faulty rows or columns. The repair solution is then stored permanently, usually by programming eFuses (lesson 7).

At each power-up, the fuse contents are loaded into repair registers in the memory, which steer the faulty address or column to the spare. Some designs also support soft repair, where MBIST runs at every boot and the repair is held in registers only. Thus, a die with a few defective cells becomes a good die, which can raise yield noticeably for chips with large memories. The cost is spare and fuse area plus a small steering delay.

10.6 Error-correcting codes

Repair handles defects found at test. Errors that occur in the field are handled by error-correcting codes (ECC). The most common scheme for on-chip memories is SECDED – single-error correction, double-error detection – based on a Hamming code with an extra overall parity bit. Check bits are computed from the data on every write and stored alongside it. On every read, the check bits are recomputed and compared; the result, called the syndrome, is zero if there is no error and otherwise points to the bit in error, which is flipped back.

r = 6 :  2^6 = 64  < 64 + 6 + 1 = 71    (not enough)
r = 7 :  2^7 = 128 >= 64 + 7 + 1 = 72   (enough)
SECDED check bits = 7 + 1 = 8   ->  a (72, 64) code, 12.5 percent overhead

## For 32 data bits: r = 6, SECDED = 7 bits -> (39, 32), about 22 percent

SECDED corrects only one bit per word. A particle strike can upset several physically adjacent cells, an event called a multi-cell upset. The column interleaving of lesson 5 places adjacent cells in different words, so such an upset becomes several single-bit errors in different words, each of which SECDED can correct. Many systems also scrub memories, reading and correcting them in the background so that single errors do not accumulate into uncorrectable double errors.

10.7 Soft errors

A soft error is a change in stored data caused by radiation, not by a defect; rewriting the cell fixes it. The main sources are alpha particles from trace radioactive impurities in packaging and solder, and atmospheric neutrons, which create charged secondary particles in silicon. If the collected charge on a storage node exceeds the critical charge of the cell, the cell flips. The soft error rate is quoted in FIT, the number of failures per billion device-hours. Because SRAM storage nodes are small, caches in servers and safety-related chips are routinely protected with ECC.

10.8 Low-voltage retention

Lowering the supply of an idle memory reduces its leakage sharply. The lowest supply at which every cell still holds its data is called the data retention voltage (DRV). It is set by the worst cell in the array, where random variation has made the hold noise margin of lesson 4 collapse first. The voltage needed for reliable reads and writes (often called Vmin) is higher than the DRV, because read stability and writability fail before hold does.

Compilers therefore offer retention or sleep modes in which the periphery is switched off and the array supply is lowered to a level above the DRV with margin, sometimes by raising the array's ground (source biasing) instead. MBIST should then include a retention test at the reduced voltage, since a weak cell may fail only in retention.

10.9 Interview questions

Why is MBIST used instead of scan for memories? The array has no scan chain, its faults include coupling and retention effects, and external testing of millions of cells would be too slow. MBIST applies algorithmic patterns at speed on chip.

Write out March C- and state its length. Either order w0; ascending r0, w1; ascending r1, w0; descending r0, w1; descending r1, w0; either order r0. It takes 10N operations.

How many check bits does SECDED need for 64 data bits? Eight: seven Hamming bits, since 2^7 is at least 64 + 7 + 1, plus one overall parity bit, giving a (72, 64) code.