Standard Cell Design

A standard-cell library is the most heavily reused piece of custom design on any chip. Each cell is drawn once, by hand or with layout automation under close supervision, and then placed millions of times by tools that never look inside it. The rules that make this possible – a fixed height, shared power rails, pins that a router can reach, and edges that may touch any other cell – are the subject of this lesson.

We build on the inverter of lesson 2, now seen as layout rather than schematic, and finish with what a library actually contains. Lesson 9 will show how the same cells are characterized into Liberty models.

Reading time: about 8 minutes.

3.1 What makes a cell "standard"

A standard cell is a pre-designed logic gate whose layout follows a common template, so that any cell can be placed next to any other in a row. The template fixes three things.

1. Height. Every cell in the library has the same height (or a whole multiple of it, for double-height cells). This lets the placer arrange cells in horizontal rows.
2. Width granularity. Cell widths are whole multiples of a placement site. In many modern libraries the site width equals the contacted poly pitch (CPP), the spacing from one gate to the next.
3. Power and well positions. The VDD and VSS rails, and the n-well and p-well regions, sit at the same height in every cell, so they connect automatically when cells abut.

Thus, the template is a contract between the library team and the implementation tool. The library team accepts some loss of density inside each cell in exchange for cells that the tool can place freely.

3.2 Cell architecture: rails, rows and tracks

Inside a cell, the VDD rail runs along the top edge and the VSS rail along the bottom edge. The PMOS transistors sit in the upper half, inside the n-well, close to VDD. The NMOS transistors sit in the lower half, close to VSS. Each rail is drawn half inside the cell, so that it is completed by the cell in the next row.

In the placement area, alternate rows are flipped vertically. Row 1 has VSS at the bottom and VDD at the top. Row 2 is mirrored, so its VDD meets the VDD of row 1 and their n-wells merge. Row 3 then shares VSS with row 2, and so on. This sharing saves one rail per row and keeps the wells continuous.

Cell height is usually quoted in tracks: the number of horizontal routing pitches of the lower metal layer that fit in the cell height. A 12-track or 9-track library has room for wide transistors and internal wiring and suits high-performance blocks. A 7.5-track or 6-track library is denser and lower in leakage but has less drive and fewer internal routing resources, so it can be harder to route. Many processes offer more than one height for this reason.

9-track height   = 9.0 x 64 nm   = 576 nm
7.5-track height = 7.5 x 64 nm   = 480 nm
## Assuming, a cell has the same width in both libraries
Area saving      = 1 - 480 / 576 = 16.7 percent

3.3 Layout of an inverter and a NAND2

Let us consider Fig. 3.1, which shows simplified layouts of an inverter and a two-input NAND placed side by side.

In the inverter, a single vertical poly stripe forms the gate of both transistors. Where poly crosses the PMOS active region it makes the PMOS, and where it crosses the NMOS active region it makes the NMOS. The left contacts connect the sources to the rails, and the right contacts are joined by a vertical M1 strip that forms the output Y.

The NAND2 shows two important layout habits. First, adjacent transistors share diffusion: the PMOS pair shares its middle contact as the output, and the NMOS pair shares its middle node without any contact at all, because that node connects only the two series transistors. Sharing diffusion reduces both area and parasitic capacitance. Second, the order of the gates is chosen so that one unbroken strip of diffusion serves each half. The classic method for finding such an order is the Euler path through the pull-up and pull-down graphs.

3.4 Pin access

A cell is useful only if the router can connect to its pins. In most libraries the pins are drawn on M1 (or on a local interconnect layer at advanced nodes) and the router reaches them with a via from the layer above. Each place on a pin where such a via can legally land is called an access point (some tools say hit point).

A pin with only one access point is fragile: if a neighbouring cell or a wire blocks that point, the pin cannot be reached. Hence, the library designer tries to give every pin several access points on different routing tracks, to spread pins across the cell width rather than bunching them, and to keep pins away from the rails. When pin access is poor, the symptom appears late, as routing violations clustered around particular cell types. Experienced PD engineers learn which cells cause this and may restrict their use or add spacing around them.

3.5 Designing for DRC-clean abutment

Every cell must be legal next to every other cell, in either orientation, without the tool checking pairs. The library achieves this through a few conventions.

• Everything on a grid. Poly stripes sit on a fixed pitch and run in one direction. Pins sit on routing tracks. At advanced nodes this regularity is required by the lithography, including multiple-patterning colour rules.
• Half-rules at the boundary. Each shape near the cell edge keeps at least half of the required spacing from the edge, so that two cells together always meet the full rule.
• Diffusion breaks. Active regions of neighbouring cells must be isolated. Depending on the process, this uses a dummy poly at the cell edge or a dedicated diffusion break.
• Well taps. The wells must be tied to their supplies to prevent latch-up. Many libraries leave taps out of logic cells and provide separate tap cells that the PD flow inserts at a fixed interval.

The library team verifies these conventions with DRC on test layouts where every cell abuts every other in both orientations, together with LVS on each cell. Thus, the absence of DRC errors at the cell boundary in a PD run is not luck; it is designed in.

3.6 What a library contains

A production library contains hundreds to a few thousand cells. Table 3.1 lists the main categories.

Each logic function comes in several drive strengths, often named X1, X2, X4 and so on, where the larger versions have wider (or more parallel) transistors. Each function and drive is also offered in several threshold-voltage flavours, commonly called ULVT, LVT, SVT (or RVT) and HVT. A lower threshold gives a faster cell with much higher leakage. Typically, the implementation tool uses high-Vt cells by default and swaps in low-Vt cells only on critical paths. Some libraries also offer channel-length variants for finer leakage control.

For each cell, the library team delivers a layout (GDS), an abstract (LEF) with pin shapes and blockages, a Liberty model per corner for timing and power, a Verilog model for simulation, and a transistor netlist (CDL or SPICE) for LVS. A memory macro, as lesson 8 shows, arrives with the same set of views.

3.7 Interview questions

Why do alternate standard-cell rows flip? So that neighbouring rows share a power rail and their wells merge. This saves one rail per row and keeps well continuity.

What does "9-track" mean for a library? The cell height equals nine pitches of the horizontal routing metal. It sets the room for transistors and internal wiring, and so the trade-off between drive, density and routability.

Why are the NMOS transistors in a NAND2 drawn with a shared, uncontacted middle node? The middle node connects only the two series transistors. Sharing diffusion without a contact saves area and reduces capacitance on that node.

What causes pin-access problems, and how does a library avoid them? Pins with few legal via landing points, pins bunched together, or pins near the rails. Libraries spread pins across tracks and give each several access points.