The CMOS Inverter and Transistor Sizing

Every circuit in this path, from the standard cell to the SRAM bitcell, is built from the same element: a pair of complementary transistors switching a node between the supply and ground. The CMOS inverter is the simplest such pair. If its behaviour is understood well – how it switches, how much noise it tolerates, and how its speed depends on transistor size – then the bitcell of lesson 4 and the sense amplifier of lesson 6 are two cross-coupled inverters with a few additions.

This lesson covers the inverter's voltage transfer characteristic, its switching threshold and noise margins, the ratio between PMOS and NMOS widths, and how delay changes with size. It ends with logical effort, a simple method for sizing a chain of gates.

Reading time: about 9 minutes.

2.1 The inverter and its transfer curve

A CMOS inverter has a PMOS transistor connected from the supply (VDD) to the output and an NMOS transistor connected from the output to ground. Both gates are tied to the input. When the input is low, the PMOS is on and the NMOS is off, so the output is pulled to VDD. When the input is high, the roles swap and the output is pulled to ground. In either steady state, one transistor is off, so no static current flows from VDD to ground. This is the reason CMOS logic dominates digital design.

The voltage transfer characteristic (VTC) plots the output voltage against the input voltage as the input is swept slowly from 0 to VDD. Let us consider Fig. 2.1.

The curve has three parts. For a low input the output is held at VDD, and for a high input it is held at 0. In between, both transistors conduct and the output falls steeply. The slope in this middle region is the gain of the inverter, and it is much larger than one. This high gain is what restores a degraded logic level back to a clean 0 or 1 after each gate.

2.2 The switching threshold

The switching threshold VM is the input voltage at which the output equals the input. It is found where the VTC crosses the line Vout = Vin. At this point both transistors are in saturation and carry the same current. For long-channel transistors, equating the two saturation currents gives:

VM = ( VTn + r (VDD - |VTp|) ) / (1 + r)          (2.1)

where  r = sqrt(kp / kn),   k = mu x Cox x (W/L)

Here VTn and VTp are the threshold voltages, mu is the carrier mobility and Cox the gate-oxide capacitance per unit area. In short-channel devices, velocity saturation changes the exact form, but the conclusion is the same: a stronger PMOS (larger r) pushes VM up toward VDD, and a stronger NMOS pushes it down toward ground.

2.3 Noise margins

A gate must tolerate some noise on its input without passing a wrong value to its output. Two points on the VTC define how much. VIL and VIH are the input voltages where the slope of the VTC equals -1. Below VIL the input is a valid low, and above VIH it is a valid high. VOL and VOH are the output levels, which for a static CMOS inverter are essentially 0 and VDD. The noise margins are:

NM_L = VIL - VOL        (noise margin for a low level)
NM_H = VOH - VIH        (noise margin for a high level)

Thus, a steep VTC with VM near the middle of the supply gives large and balanced noise margins. Lesson 4 uses the same idea, in the form of the butterfly curve, to measure how stable a bitcell is during a read.

2.4 The beta ratio

The beta ratio is the ratio of PMOS to NMOS strength, usually expressed as a width ratio Wp/Wn for equal channel lengths. Electrons are more mobile than holes, so for the same width an NMOS carries more current than a PMOS. In older bulk processes the electron-to-hole mobility ratio was roughly 2 to 3, so a symmetric inverter – one with VM at VDD/2 and equal rise and fall delays – needed the PMOS about two to three times wider. In many modern processes the ratio is smaller, and the library team picks the ratio from simulation.

## Case 1: kp = kn (PMOS widened to compensate mobility), so r = 1
VM = (0.3 + 1 x 0.7) / 2                = 0.50 V

## Case 2: Wp = Wn, and assuming mu_n = 2 x mu_p, so kp/kn = 0.5
r  = sqrt(0.5)                          = 0.707
VM = (0.3 + 0.707 x 0.7) / 1.707        = 0.47 V

2.5 Delay versus size

For delay, each transistor can be modelled as a switch with an equivalent on-resistance R in series. The output node has a capacitance C made of the gate's own drain capacitance (its intrinsic or self-loading capacitance) plus the external load from wires and the next gates. The propagation delay of a step input is then approximately:

tp = 0.69 x R x C                                  (2.2)

Let us scale both transistors of an inverter by a factor S. The resistance falls to R/S. The intrinsic capacitance rises to S times its value, because the drain areas grow with width. The input capacitance also rises by S. Writing Cint for the intrinsic capacitance of the unit inverter and Cext for the external load:

tp = 0.69 x (R/S) x (S x Cint + Cext)
   = 0.69 x R x Cint x ( 1 + Cext / (S x Cint) )   (2.3)

Two conclusions follow from (2.3). First, the term 0.69 R Cint is the intrinsic delay, and it does not depend on S. An unloaded inverter is no faster when it is made bigger. Second, upsizing helps only by reducing the effect of the external load, and the improvement saturates once S Cint is much larger than Cext. Meanwhile, the larger inverter presents S times more input capacitance to the gate driving it. Thus, making one gate bigger can slow down the previous one, and sizing must be considered along a path.

2.6 Logical effort and the FO4 delay

Logical effort is a method, introduced by Sutherland, Sproull and Harris, that makes path sizing a matter of simple arithmetic. It expresses the delay of a gate in units of tau, the delay of an ideal inverter driving an identical inverter with no parasitics:

d = g x h + p                                      (2.4)

g = logical effort   (input cap of the gate / input cap of an inverter
                      that delivers the same output current)
h = electrical effort = Cout / Cin   (the fanout)
p = parasitic delay  (from the gate's own diffusion capacitance)

For an inverter, g = 1 and p is approximately 1. Assuming a PMOS-to-NMOS mobility ratio of 2, a NAND2 has g = 4/3 and a NOR2 has g = 5/3. The NOR is worse because its series transistors are PMOS, which must be made wide.

The delay of an inverter driving four copies of itself is called the fanout-of-four (FO4) delay. From (2.4) it is 1 x 4 + 1 = 5 tau. FO4 is widely used as a process-independent unit: designers describe a processor cycle as "so many FO4", which lets them compare designs across technology nodes.

For a path of N stages, the path effort is F = G x B x H, where G is the product of the logical efforts, H is the ratio of final load to first input capacitance, and B accounts for branching. The delay is lowest when every stage bears the same effort, F to the power 1/N. With typical parasitics, the best stage effort is close to 4, which is why fanout-of-four appears so often in buffer chains and clock trees.

N = 1 :  stage effort 64     D = 1 x 64 + 1        = 65 tau
N = 2 :  stage effort 8      D = 2 x 8  + 2        = 18 tau
N = 3 :  stage effort 4      D = 3 x 4  + 3        = 15 tau   (3 FO4)
N = 4 :  stage effort 2.83   D = 4 x 2.83 + 4      = 15.3 tau

2.7 Interview questions

Why does a CMOS inverter draw almost no static current? In either stable state one of the two transistors is off, so there is no conducting path from VDD to ground. Current flows only while switching, plus a small leakage current.

What is the switching threshold, and how do you move it? It is the input voltage where Vout equals Vin. Making the PMOS stronger relative to the NMOS raises it, and making the NMOS stronger lowers it.

Does upsizing an unloaded inverter make it faster? No. Resistance falls by the same factor that self-capacitance rises, so the intrinsic delay stays the same. Upsizing helps only when a large external load dominates.

What is FO4 and why is it used? It is the delay of an inverter driving four identical inverters. Because it scales with the process, it is a convenient unit for comparing logic depth and cycle time across technologies.