What Custom and Memory Design Is

Most of a modern chip is built from standard cells that a synthesis tool picks and a place-and-route tool arranges. A smaller but very important part is drawn, sized and verified by hand, or generated by special tools, because the automatic flow cannot reach the density, speed or behaviour that is required. This is called custom design, and memories are its largest and most visible product.

This lesson places custom and memory design next to the standard-cell flow, lists where custom work still matters, and shows how its results appear to a physical design (PD) engineer: as hard macros in a floorplan. The rest of the path builds on this picture, from a single inverter (lesson 2) to memory test and repair (lesson 10).

Reading time: about 9 minutes.

1.1 Three ways to build a circuit

Let us consider a block that adds two 32-bit numbers. There are three broad ways to implement it.

• Full-custom – an engineer draws the schematic, chooses the width of every transistor, and draws the layout polygon by polygon. Nothing is pre-made except the process rules.
• Standard-cell (cell-based) – the adder is written in RTL, synthesis maps it to cells from a pre-characterized library (NAND2, flip-flops and so on), and the implementation tool places and routes those cells. The designer never sees a transistor.
• Semi-custom – a mix of the two. For example, a datapath might be built from library cells but placed by hand in a regular bit-sliced pattern, or a few critical gates might be custom-drawn and dropped into an otherwise synthesized block. Gate arrays and structured ASICs, where the transistors are pre-fabricated and only the wiring is customized, are older forms of the same idea.

Table 1.1 compares them. The trade-off is effort against quality of result.

Thus, full-custom is not an old-fashioned method that the flow has replaced. It is the method used where a circuit is repeated so many times, or is so sensitive, that the extra effort pays for itself.

1.2 Where custom design still matters

In a typical system-on-chip (SoC), custom design effort is concentrated in a few places.

1. SRAM bitcells and arrays. A cache of 1 MB holds more than eight million bitcells. Saving a few percent of bitcell area saves far more silicon than any optimization of random logic. The 6T bitcell is the subject of lesson 4.
2. Register files. Processor register files need several read and write ports at high speed. They are often built from special multi-port cells, which lesson 7 describes.
3. The standard cells themselves. Every NAND2 and flip-flop in a library was designed by hand, once, by a library team. Lesson 3 covers how.
4. Datapaths. Adders, multipliers and shifters in high-performance processors are sometimes hand-placed or partially custom so that the bit slices line up and wires stay short.
5. IO cells. Pads must survive electrostatic discharge, drive board-level loads and shift voltage levels. They are drawn as custom cells and delivered as a library.
6. Analog and mixed-signal blocks. Phase-locked loops, data converters and SerDes circuits are custom by nature. They are outside the scope of this path, although they reach the floorplan in the same way as memories.

The common thread is repetition or sensitivity. A bitcell is repeated millions of times, a library cell is used millions of times across many designs, and an IO or analog block is sensitive to every parasitic. In each case, careful work at the transistor level is multiplied many times over.

1.3 Why memories need their own discipline

Memories differ from random logic in three ways that shape everything in this path.

• Density. On-chip SRAM frequently occupies a large share of die area – in many processors and AI accelerators it is the single largest consumer. Bitcells are therefore drawn with special, tighter rules called push rules, which lesson 4 explains.
• Analog behaviour inside a digital block. A memory read does not produce a full-swing logic level on the bitline. It produces a small voltage difference that a sense amplifier must detect (lesson 6). Timing is controlled by self-timed circuits, not by a simple chain of gates.
• Test and yield. A large array is very likely to contain a few defective cells. Memories are therefore tested by built-in self-test and repaired with spare rows and columns (lesson 10).

Because of these differences, memories are rarely drawn from scratch for each chip. Usually, the foundry or an IP vendor supplies a memory compiler – a generator that tiles pre-drawn leaf cells into a macro of the requested size and produces all the views the flow needs. Lesson 8 is devoted to this.

1.4 How memories appear in a floorplan

To a PD engineer, a memory is a hard macro: a fixed rectangle with a known size, fixed pin locations and internal routing that must not be touched. The implementation tool does not see its transistors. It sees an abstract view (LEF) for placement and routing and a timing view (Liberty) for analysis. Let us consider Fig. 1.1.

Several habits are visible in the figure, and lesson 8 explains each of them in detail.

• Macros are usually pushed to the edges or corners of the core so that the standard-cell area stays one large, unbroken region.
• Pins face the logic that uses them. A macro with its pins against the core boundary would force every signal to route around it.
• A halo (also called a keep-out margin) is reserved around each macro. Standard cells are not placed in it, which leaves room for pin access and for the power connections into the macro.
• The macro is a routing obstruction on its internal metal layers. Signals may usually pass over it only on the upper layers that the macro abstract leaves free.

Capacity   = 32 x 1024 bytes x 8 bits      = 262,144 bits
## Assuming, an illustrative bitcell area of 0.10 square micrometres
Cell area  = 262,144 x 0.10 um^2            = 26,214 um^2
## Assuming, the bitcells fill 60 percent of the macro (array efficiency);
## decoders, sense amplifiers and control fill the rest
Macro area = 26,214 / 0.60                  = about 43,700 um^2 (0.044 mm^2)

1.5 Who does what

Memory and custom work is spread across several roles. In a small company one person might hold more than one of them.

• Circuit (memory) designer – designs the bitcell periphery: decoders, sense amplifiers, timing circuits. Works in SPICE-level simulation, including Monte Carlo for variation.
• Custom layout engineer – draws the leaf cells and the standard cells, meets design rules, and runs layout-versus-schematic (LVS) checks.
• Memory compiler developer – turns the leaf cells into a generator that produces any legal size, with all its views.
• Characterization engineer – simulates the cells and macros across corners and writes the Liberty timing and power models (lesson 9).
• DFT and test engineer – plans memory built-in self-test (MBIST) and repair (lesson 10).
• PD engineer – the consumer. Chooses macro configurations with the architects, places the macros, connects power and closes timing around them.

A PD engineer does not need to design a sense amplifier. However, a PD engineer who understands why a macro has a certain aspect ratio, why its setup time is large, or why its power pins sit where they do will make better floorplan decisions and ask better questions of the memory team.

1.6 How this path is organized

Lessons 2 and 3 cover the foundations: the CMOS inverter and transistor sizing, and how standard cells are built. Lessons 4 to 6 build an SRAM from the bitcell upward: the cell, the array, and the periphery with its timing. Lesson 7 surveys register files and other memory types. Lessons 8 and 9 move to the views a PD engineer receives: compiler outputs and Liberty characterization. Lesson 10 closes with test, repair and reliability.

1.7 Interview questions

What is the difference between full-custom and standard-cell design? In full-custom design, the engineer chooses every transistor and draws every polygon. In standard-cell design, synthesis maps RTL to pre-characterized library cells and an implementation tool places and routes them. Full-custom gives the best density and speed at a high cost in effort and turnaround.

Why are memories not synthesized from flip-flops? A flip-flop uses many more transistors and far more area per bit than a 6T bitcell, and a bank of flops also burns more clock power. For anything beyond a small number of bits, a memory macro is far denser and lower in power.

What does a PD engineer receive for a memory macro? Typically a LEF abstract for placement and routing, Liberty files for timing and power at each corner, a Verilog model for simulation, a GDS (or a placeholder) for final merge, and a datasheet.

Why do macros usually go at the edges of the core? To keep the standard-cell region contiguous, to avoid narrow channels that cause congestion, and to let the pins face inward toward the logic that uses them.