ICC2: 14. Extraction and signoff correlation Cheat Sheet

This stage covers extraction and signoff correlation: parasitic technology setup per corner, route-aware estimation settings, confirming routing is final, timing update after extraction, parasitic and constraint hand-off to the signoff timer, and rail analysis.

Sanity check cheat sheet

One row per command card. Read left to right: the check, the command that answers it, then what a healthy result, a result to review and a hard stop look like.

Card	Check and when	Command	Healthy	Review	Hard stop
X-01	Parasitic technology per corner Before timing signoff	`set_parasitic_parameters`	Every corner has its own TLUPlus data; no emulation files left in a signoff corner.	Two corners share one parasitic file, agreed with the extraction owner and recorded.	A corner has no parasitic data.
X-02	Pre-route estimation settings Before correlation	`set_app_options -name opt.common.enable_rde -value true` `set_app_options -name opt.common.use_route_aware_estimation -value auto`	Route-driven estimation on where the node needs it; route-aware setting recorded.	Both settings are present. Route-driven estimation takes precedence and the route-aware setting is ignored, so record which one applies.	The estimation settings differ between the runs being compared.
X-03	Routing is final Before extraction	`check_routes` `check_lvs`	No open nets or shorts, so extraction sees the final wiring.	Remaining items are approved waivers.	Opens or shorts present.
X-04	Fill in extraction After metal fill	`set_extraction_options -real_metalfill_extraction floating`	Real fill is extracted; virtual fill assumptions removed.	Fill modelled as floating, grounded by methodology decision.	Fill present but unseen by extraction.
X-05	Timing update and results After extraction	`update_timing` † `report_timing` `check_timing` †	Timing is current with the new parasitics; slack within the project budget.	Slack worse than before extraction but inside budget.	Stale timing, or slack beyond budget.
X-06	Parasitic hand-off Before signoff timer	`write_parasitics` † `read_parasitics` †	One file per corner, named by scenario, and re-read cleanly.	File count differs from corner count by agreement.	Missing corner file, or parse errors.
X-07	Constraints match signoff Before correlation	`write_sdc` `write_script -format icc2`	Both timers read the same constraints; latency offsets captured in the script file.	Differences explained by tool-specific constructs.	Signoff run uses older constraints.
X-08	Rail analysis After CTS and routing	`analyze_rail -voltage_drop static -nets {VDD VSS}` `analyze_rail -electromigration`	Drop and current violations within the project budget; ideal sources defined.	Violations isolated to few instances with a fix plan.	Drop beyond budget, or no voltage source defined.
X-09	Missing vias and pins Before rail analysis	`set_missing_via_check_options` `analyze_rail -check_missing_via -voltage_drop static`	No unconnected pin shapes or missing vias on analysed nets.	Findings only inside macros, each approved.	Unconnected pins left in the analysed grid.

Command cheat sheet

ICC2 commands. Angle brackets are placeholders, and values shown are examples, not project limits. A dagger (†) marks a command the notes behind this book do not fully cover; it is shown without options, so confirm it with man or help in your release.

Extraction settings
`set_parasitic_parameters`	Associates parasitic technology data with each timing corner. Changes the session; record it.
`set_extraction_options -real_metalfill_extraction floating`	Real metal fill taken into extraction as floating metal. Changes the session; record it.
`set_app_options -name opt.common.enable_rde -value true`	Route-driven estimation during final optimisation. Changes the session; record it.
`set_app_options -name opt.common.use_route_aware_estimation -value auto`	Global-route-based estimation, enabled only when layer resistance varies. Changes the session; record it.
Routing readiness
`check_routes`	Routing DRC, open nets and antenna findings in zroute.err.
`check_lvs`	Shorts, opens and floating shapes on signal, clock and PG nets.
`report_design -routing`	Final wiring statistics: shape counts and wire length.
Parasitic files
`write_parasitics` †	Writes extracted parasitics for the signoff timer.
`read_parasitics` †	Loads parasitics back for annotation checks.
Timing settings that must match
`write_sdc`	Constraints written for the signoff timer.
`write_script -format icc2`	Constraints including latency offsets that write_sdc does not capture.
`report_clock_qor`	Clock skew and latency summary to compare between tools.
In-tool and signoff timing
`update_timing` †	Refreshes timing with the current parasitics.
`report_timing`	Worst paths for comparison with the signoff timer on the same parasitics.
`check_timing` †	Constraint and annotation completeness findings.
`report_constraints -max_transition`	Design rule constraint violations for transition.
Rail analysis
`create_taps -supply_net VDD -top_pg`	Ideal voltage sources from top-level PG pins. Changes the session; record it.
`analyze_rail -voltage_drop static -nets {VDD VSS}`	Static IR drop with results loaded into the session.
`analyze_rail -electromigration`	PG current density violations.
`analyze_rail -script_only`	Generates analysis scripts and input files without running.
`analyze_rail -check_missing_via -voltage_drop static`	Missing vias and unconnected pin shapes alongside drop.