ICC2: Floorplan, macro and pins Cheat Sheet

This stage covers establishing the floorplan: die and core geometry, legality and blockages, macro placement, pin placement, and voltage areas for multivoltage designs, ending with a floorplan handoff snapshot.

Sanity check cheat sheet

One row per command card. Read left to right: the check, the command that answers it, then what a healthy result, a result to review and a hard stop look like.

Card	Check and when	Command	Healthy	Review	Hard stop
F-01	Die and core geometry After floorplan	`initialize_floorplan` † `write_floorplan`	Die and core extents equal the specification, and the floorplan writes without error.	A core offset that differs by a small amount. Snapping to the site or track grid is one possible cause.	Die size different from the specification, which changes every downstream step.
F-02	Floorplan legality After floorplan	`check_legality` `check_design` †	No violations for the recorded checks. Utilisation is within the project budget.	Effective utilisation noticeably above target, which means blockages remove more area than planned.	Off-grid cells, illegal row orientation, or utilisation over the project limit in a bound or region.
F-03	Keepouts and blockages After macro placement	`get_placement_blockages` `report_bounds`	Each blockage and bound is in the written plan, with the planned type and shape.	A soft blockage that the plan expected to be hard.	A hard blockage over an area the plan needs, or a bound missing from the plan.
F-04	Macro placement After macro placement	`get_cells -hier <macro_pattern>` `check_legality`	Macro count equals the macro list, with no overlap, no off-grid placement and no violation.	Fixed cells that the specification does not mention, such as preplaced taps.	A macro unplaced, overlapping, outside the core, or in a channel below the budget width.
F-05	Pin placement After pin placement	`place_pins` † `check_pin_placement` †	No violations. Pin side and order match the pin plan where one is entered.	Pins placed but not yet matched to the parent plan in a hierarchical flow.	Unplaced or overlapping pins, pins off track, or pins on a side the plan does not allow.
F-06	Voltage areas After floorplan, for multivoltage designs	`report_voltage_areas -verbose` `check_mv_design`	Each voltage area matches its power domain, shape and guard band in the plan.	Overlapping areas whose stacking order was intended.	A domain without an area, an area outside the core, or an MV violation.
F-07	Floorplan handoff snapshot Before power planning	`write_floorplan` `write_def` `save_block`	Floorplan files and the saved block exist, and match the handoff record.	Routing blockages not captured by the DEF; write_floorplan covers them.	A handoff file missing, or a save that predates the last floorplan edit.

Command cheat sheet

ICC2 commands. Angle brackets are placeholders, and values shown are examples, not project limits. A dagger (†) marks a command the notes behind this book do not fully cover; it is shown without options, so confirm it with man or help in your release.

Floorplan creation and exchange
`initialize_floorplan` †	Creates die, core and site rows for the block. Changes the session; record it.
`read_def <block.def>`	Brings an existing floorplan in from DEF, keeping existing floorplan data by default.
`read_def -syntax_only <block.def>`	A syntax check of the DEF, with no change to the block.
`check_duplicates -remove`	Removes duplicate shapes and vias after the DEF read.
`write_floorplan`	Writes the floorplan, including routing blockages that DEF output does not reproduce.
`write_def`	Writes the DEF. For cut metal shapes, write_def -version 5.8 is required.
Keepouts and blockages
`create_keepout_margin -outer {<l> <b> <r> <t>} <macro>`	A hard outer keepout around the macro. Changes the session; record it.
`create_keepout_margin -type soft -outer {<l> <b> <r> <t>} <macro>`	A soft outer keepout around the macro. Changes the session; record it.
`create_placement_blockage -boundary {{<x1> <y1>} {<x2> <y2>}} -type hard`	One hard placement blockage in the rectangle. Changes the session; record it.
`get_placement_blockages`	The placement blockages of the block.
`remove_placement_blockages -all`	Removes every placement blockage. Changes the session; record it.
`create_routing_blockage -boundary {{<x1> <y1>} {<x2> <y2>}} -net_types signal -layers <layer>`	A routing blockage for signal nets on the layer. Changes the session; record it.
`create_bound -name <b> -boundary {<x1> <y1> <x2> <y2>} <cells>`	A soft move bound for the cells. Add -type hard for a hard bound.
`report_bounds`	Every bound with its type and shape.
Legality
`check_legality`	Placement legality violations for the block.
`check_legality -cells <cells>`	The same check limited to the given cells.
`legalize_placement`	Moves cells to legal positions. Changes the session; record it.
Macros
`get_cells -hier <macro_pattern>`	The macros that match the pattern, to compare with the macro list.
`create_placement -floorplan`	Placement used in the hard-macro flow. Changes the session; record it.
`set_macro_constraints` †	Macro placement constraints for the macro placer. Changes the session; record it.
Pins
`set_block_pin_constraints` †	Block-level pin constraints such as sides and layers. Changes the session; record it.
`set_individual_pin_constraints` †	Constraints for single pins. Changes the session; record it.
`place_pins` †	Places the block pins under the constraints. Changes the session; record it.
`check_pin_placement` †	Pin placement violations such as overlap, off-track and unplaced pins.
Voltage areas
`create_voltage_area -power_domains {<pd>} -name <va> -region {{<x1> <y1>} {<x2> <y2>}}`	A voltage area for the power domain. Changes the session; record it.
`get_voltage_areas`	The voltage areas of the block.
`report_voltage_areas -verbose`	Voltage areas with stacking order and well supply nets.
`check_mv_design`	Multivoltage violations after the areas are created.
`remove_voltage_areas -all`	Removes every voltage area. Changes the session; record it.