This stage covers building the power network: logical PG connections, tap and boundary cells, the PG mesh and standard-cell rails, missing vias and shorts, rail analysis, and the routing resource left for the router.
Sanity check cheat sheet
One row per command card. Read left to right: the check, the command that answers it, then what a healthy result, a result to review and a hard stop look like.
| Card | Check and when | Command | Healthy | Review | Hard stop |
|---|---|---|---|---|---|
| P-01 | Logical PG connections After import or UPF commit |
connect_pg_net -automaticcheck_mv_design -pg_pin |
Every PG and tie pin connects to the intended supply net, and the pin check reports no findings. | A pin left out of the automatic derivation, or a manual connection that overrides the UPF intent without a note. | Any PG pin on the wrong supply net, or a PG conflict left unresolved at commit. |
| P-02 | Tap and boundary cells After the floorplan, before PG structure |
create_tap_cells -lib_cell <tap_lib>/<tap_cell> -distance <um>check_boundary_cells |
Taps meet the project tap distance rule and the boundary check lists no gaps, wrong cells or wrong orientation. | Extra taps beside macros or blockages, or boundary rows shorter than the rule allows. | Missing boundary or corner cells, or tap spacing that breaks the rule where cells will be placed. |
| P-03 | Rings and mesh construction After connections and tap cells |
create_pg_mesh_pattern <pattern> †compile_pg { <PG strategies> } |
Geometry matches the PG specification, the top-level structure is closed, and both nets cover the whole core. | A strap pitch that leaves a wide strip with no strap, often beside macros. | A missing ring side, nets swapped on a strap pair, a layer the specification forbids, or a short between nets. |
| P-04 | Standard-cell rails and macro pins After the mesh |
create_pg_std_cell_conn_pattern <pattern> †compile_pg { <PG strategies> } |
Every row has a rail and every macro PG pin has a connection to the mesh. | Connections that land on a different layer from the plan. | A row with no rail, or a macro PG pin with no connection. |
| P-05 | Missing vias and unconnected pins After the PG structure is complete |
set_missing_via_check_optionsanalyze_rail -check_missing_via |
No missing via between overlapping PG shapes and no pin shape detached from an ideal voltage source. | Detached pin shapes on cells that are intentionally unpowered, which must be listed and explained. | A missing via where same-net PG wires overlap, or a macro PG pin shape with no supply path. |
| P-06 | PG shorts and opens After vias are in |
check_lvs -checks shortcheck_lvs -checks open |
No shorts or opens on the supply nets, and the same command form is used in every run. | Opens reported only because terminals are treated as unconnected voltage sources by default. | Any short between supply nets, or between a supply wire and a signal net, or any open on a supply net. |
| P-07 | Early rail analysis After the mesh, repeated after placement |
analyze_rail -voltage_drop static -nets {VDD VSS}analyze_rail -electromigration |
Voltage drop and current density meet the project budget on every supply net, with the scenario recorded. | Hotspots near macros or far from supply, where a stronger mesh or more taps is the usual lever. | Drop or current density above the project budget with no grid change planned. |
| P-08 | Routing resource left by the grid After the grid is final |
set_ignored_layers -min_routing_layer <layer> -max_routing_layer <layer>check_routability -check_pg_blocked_ports true |
Layer limits match the plan, and no standard-cell or macro port is blocked by PG shapes. | One layer carrying much more PG than its neighbours, which pushes signal routing elsewhere. | Blocked ports caused by PG shapes, or layer limits that leave the router too few layers. |
Command cheat sheet
ICC2 commands. Angle brackets are placeholders, and values shown are examples, not project limits. A dagger (†) marks a command the notes behind this book do not fully cover; it is shown without options, so confirm it with man or help in your release.
| PG net connection | |
|---|---|
connect_pg_net -automatic | Derives logical PG and tie connections from the UPF. Changes the session; record it. |
connect_pg_net -net VDD [get_pins */vdd] | Connects the listed pins to one net by hand, for pins the UPF does not cover. Changes the session; record it. |
connect_pg_net -pg | Connects power and ground pins only, leaving tie pins alone. Cannot be combined with an object list. |
resolve_pg_nets -check_only | Checks UPF consistency and finds PG conflicts without changing anything. |
check_mv_design -pg_pin | Reports PG pin connection violations against the power intent. |
| Tap and boundary cells | |
create_tap_cells -lib_cell <tap_lib>/<tap_cell> -distance <um> | Inserts a tap array at the given distance in every row. Changes the session; record it. |
create_tap_cells -lib_cell <tap_lib>/<tap_cell> -distance <um> -pattern stagger | Inserts a checkerboard tap pattern, where the distance is a larger multiple of the diffusion-to-tap rule. |
set_boundary_cell_rules -left_boundary_cell <cell> -right_boundary_cell <cell> | Records the end-cap requirements that the compile step follows. |
compile_boundary_cells -add_placement_blockage | Inserts boundary and corner cells, and creates the placement blockages the jog rules ask for. Changes the session; record it. |
check_boundary_cells | Reports missing, wrong or misoriented boundary and corner cells, and short rows. |
| PG structure | |
compile_pg { <PG strategies> } | Builds or rebuilds the top-level PG structure from the strategies. Changes the session; record it. |
create_pg_mesh_pattern <pattern> † | Defines a mesh pattern for use in a strategy. |
set_pg_strategy <strategy> † | Binds a pattern to a target region and nets before compile_pg. |
create_pg_std_cell_conn_pattern <pattern> † | Defines the rail pattern that connects standard-cell PG pins. |
create_pg_macro_conn_pattern <pattern> † | Defines how macro PG pins connect to the mesh. |
remove_shapes [get_shapes -filter "net_type==power"] | Strips obsolete power shapes before a rebuild. Repeat for ground, and for vias. Changes the session; record it. |
| Vias, shorts and opens | |
set_missing_via_check_options | Configures the missing-via check. Save the block before running the check. |
analyze_rail -check_missing_via | Lists missing vias and unconnected pin shapes. With RedHawk-SC it must be combined with -voltage_drop. |
check_lvs -checks short | Reports shorts on signal, clock and PG nets. At most the default number per type is listed. |
check_lvs -checks open | Reports open nets, with PG terminals treated as unconnected sources by default. |
check_lvs -check_child_cells true | Adds shorts between top-level and child-cell shapes, which are skipped by default. |
check_pg_connectivity † | Checks PG net connectivity of the power grid. |
| Rail analysis | |
set_app_options -name rail.product -value redhawk | Selects the rail analysis engine. Needs the matching licences. Changes the session; record it. |
analyze_rail -voltage_drop static -nets {VDD VSS} | Static voltage drop on the named nets, for the current scenario only by default. |
analyze_rail -electromigration | PG electromigration analysis from the same setup. |
close_rail_result | Closes the open rail result so the next run does not overwrite it. |
| Routing resource and checkpoint | |
set_ignored_layers -min_routing_layer <layer> -max_routing_layer <layer> | Sets the routing layer limits used by estimation and congestion. Set before placement. Changes the session; record it. |
report_ignored_layers | Prints the layer limits now in force. |
check_routability -check_pg_blocked_ports true | Adds a check for ports blocked by PG shapes to the default routability checks. |
save_block -as <block>/<label> | Saves a labelled version of the block as the checkpoint to return to. Writes to the library. |