This stage covers the gate before clock tree synthesis: clock definitions and uncertainty, ideal network removal, clock routing rules and layer limits, the CTS cell list, interclock balancing, and protected clock objects, finishing with the readiness gate and a reference to the clock_opt run itself.
Sanity check cheat sheet
One row per command card. Read left to right: the check, the command that answers it, then what a healthy result, a result to review and a hard stop look like.
| Card | Check and when | Command | Healthy | Review | Hard stop |
|---|---|---|---|---|---|
| K-01 | Clock definitions Before CTS setup |
report_clocks †check_timing †get_clocks |
Every planned clock is listed in every mode, and generated clocks have sources. | Latency or uncertainty in the constraints that the clock plan does not list. | A planned clock is missing, or a generated clock has no source. |
| K-02 | Ideal state and uncertainty Before CTS |
remove_ideal_networkset_clock_uncertainty -setup -rise -fall <v> [get_clocks <clk>] |
Ideal network settings are removed before CTS, and uncertainty reflects the skew budget in the plan. | Uncertainty left at a pre-CTS value after clocks become propagated. | An ideal network still set on a clock that CTS must build. |
| K-03 | Clock routing rules Before CTS |
create_routing_rule <rule> -multiplier_width <m>set_clock_routing_rules -min_routing_layer <layer> -max_routing_layer <layer> |
Each clock net class has a rule and a layer range, and the track cost fits the routing budget. | Wide rules on sink nets, which can use too much routing resource. | A net class the plan wants ruled has none, or a rule the routing budget cannot afford. |
| K-04 | Root net and level rules After K-03 |
set_clock_tree_options -root_ndr_fanout_limit <n>set_app_options -list {cts.compile.topological_ndr true} |
The fanout limit and level-based rule are set on purpose and match the NDR plan. | A small fanout limit, which gives more root nets and raises congestion risk. | Rules applied at different levels with gaps, where the plan needs a continuous rule. |
| K-05 | Clock cell lists After K-03 |
set_lib_cell_purpose -include cts <lib_cells>get_lib_cells -filter valid_purposes=~*cts* |
The CTS cell list is deliberate, and every listed cell exists in every scenario. | Cells absent from the list for a reason, such as library trimming. | No usable buffer, inverter or clock gate remains for CTS, or a listed cell is missing in a scenario. |
| K-06 | Interclock balancing After K-01 |
create_clock_balance_group -name <group> -objects [get_clocks {<clk1> <clk2>}]report_clock_balance_groups |
Clocks that exchange data are in a balance group with offsets from the plan. | A group made only to silence a report, or a generated clock inside a group. | Clocks with interclock paths and no balancing plan, when the project requires one. |
| K-07 | Clock tree pins and gates After K-01 |
get_clock_tree_pins -clocks <clk>get_clock_tree_pins -filter is_on_ICG -clocks <clk> |
Pin lists match the clock plan, and every clock gate is on a planned tree. | Extra pins that nobody asked for. | Data pins listed as clock tree pins, or a planned gate missing from the tree. |
| K-08 | Protected clock objects After K-05 |
report_dont_touchreport_size_only -all |
Each protected object inside the clock network is on the clock plan with an owner. | A few protections on gates the plan accepts as fixed. | A dont_touch on a cell or net that CTS must resize or buffer, with no plan for it. |
| K-09 | CTS readiness gate Last check before CTS |
check_design †check_legalitycheck_timing † |
The design check reports no errors, placement is legal, and timing checks show only expected ideal-clock warnings. | Warnings with an owner, such as a tight skew target the project accepts. | Any design check error, or any legality violation. |
Command cheat sheet
ICC2 commands. Angle brackets are placeholders, and values shown are examples, not project limits. A dagger (†) marks a command the notes behind this book do not fully cover; it is shown without options, so confirm it with man or help in your release.
| Clock definitions and ideal state | |
|---|---|
report_clocks † | The clocks with their waveforms and uncertainties. |
check_timing † | Constraint warnings, including clock and ideal-clock findings. |
get_clocks | The clock objects in the current mode. |
set_clock_uncertainty -setup -rise -fall <v> [get_clocks <clk>] | Sets setup uncertainty to model skew before CTS. Changes the session; record it. |
set_ideal_network [all_fanout -flat -clock_tree] | Marks clock networks ideal. Run it per mode, and remove it before CTS. |
remove_ideal_network | Removes ideal network marking. Run before CTS. Changes the session; record it. |
| Clock routing rules | |
create_routing_rule <rule> -multiplier_width <m> | A rule with widths scaled from the default. Changes the session; record it. |
create_routing_rule <rule> -widths {<layer> <w>} | A rule with explicit widths per layer. Changes the session; record it. |
set_clock_routing_rules -rules <rule> | Assigns the rule to clock nets. Changes the session; record it. |
set_clock_routing_rules -min_routing_layer <layer> -max_routing_layer <layer> | Limits clock routing layers for every clock tree. Changes the session; record it. |
set_clock_routing_rules -clocks <clk> -net_type root -min_routing_layer <layer> -max_routing_layer <layer> | A layer range for the root nets of one clock. |
set_clock_tree_options -root_ndr_fanout_limit <n> | Sets the fanout limit that identifies root nets. Changes the session; record it. |
set_app_options -list {cts.compile.topological_ndr true} | Orders NDRs by tree level, root over internal over sink. Changes the session; record it. |
| Clock cell lists | |
set_lib_cell_purpose -exclude cts <lib_cells> | Removes cells from CTS use. Changes the session; record it. |
set_lib_cell_purpose -include cts <lib_cells> | Allows the cells for CTS. |
get_lib_cells -filter valid_purposes=~*cts* | The cells valid for CTS now. |
report_target_library_subset | Library subset restrictions that may limit clock cells. |
| Balancing and clock tree pins | |
create_clock_balance_group -name <group> -objects [get_clocks {<clk1> <clk2>}] | Groups clocks for delay balancing. Generated clocks cannot be balanced against others. |
derive_clock_balance_constraints -slack_less_than <v> | Finds clocks with interclock paths worse than the slack and groups them. |
report_clock_balance_groups | Lists the groups and their offsets. |
get_clock_tree_pins -clocks <clk> | The pins on the clock tree of the named clock. |
get_clock_tree_pins -filter is_on_ICG -clocks <clk> | Only the clock tree pins on clock-gating cells. |
| Protected objects | |
report_dont_touch | dont_touch settings, including those inside the clock network. |
report_size_only -all | size_only settings. |
set_dont_touch_network [get_clocks <clk>] -clock_only | Protects the clock network only. Changes the session; record it. |
| Readiness and after CTS (reference) | |
check_design † | The design check before the CTS stage. |
check_legality | Legality of the placement CTS starts from. |
clock_opt -from build_clock -to route_clock | Builds and routes the clock trees. Changes the session; record it. |
report_clock_qor | Latency, skew, DRC violations, area and buffer count after CTS. |
report_clock_timing -type skew | Skew report after CTS. |