ICC2: 9. CTS and post-CTS Cheat Sheet

This stage covers the checks around clock tree synthesis: confirming prerequisites before clock_opt, judging the clock_opt run and QoR report, checking skew and balance groups, verifying clock routes and NDR, and reading CCD, propagated-clock timing and clock power.

Sanity check cheat sheet

One row per command card. Read left to right: the check, the command that answers it, then what a healthy result, a result to review and a hard stop look like.

Card	Check and when	Command	Healthy	Review	Hard stop
C-01	CTS prerequisites Before clock_opt	`check_design` † `report_ignored_layers` `report_clock_balance_groups`	Every functional clock is defined, layer limits match the plan, and balance groups are as intended.	Generated clocks sit in a balance group, which the tool cannot balance against other clocks.	A clock in the constraints has no definition, or the layer limits differ from the technology plan.
C-02	CTS run and log After clock_opt	`clock_opt -from build_clock -to route_clock` `clock_opt -from final_opto`	Both stages finish with no errors, and every warning is read and either fixed or explained.	Warnings on dont_touch cells or nets, which can limit balancing and sizing of clock cells.	Any error message, or a run that leaves clocks ideal or clock nets unrouted.
C-03	Clock QoR summary After C-02	`report_clock_qor` `report_clock_qor -type drc_violators` `report_clock_qor -type latency`	Latency, area and buffer count match the plan, and transition and capacitance violators are within the project budget.	Violators only on dont_touch or pre-routed nets that CTS may not be able to fix.	A clock with no sinks in the report, or clock DRC violators beyond the project budget.
C-04	Skew and balance groups After C-03	`report_clock_qor -type local_skew` `report_clock_qor -type balance_groups` `report_clock_timing -type skew`	Local skew and achieved group offsets meet the budget in every scenario reported.	Skew meets the budget in one scenario while another scenario misses it.	Skew beyond a target the flow enforces, or a balance group with no active sinks.
C-05	Interclock skew and robustness After C-04	`report_clock_timing -type interclock_skew` `report_clock_qor -type robustness -robustness_corner <corner>`	Interclock skew is within budget, and sink latency ratios against the robustness corner are as planned.	A few sinks with a latency ratio far from the rest, which can hide corner sensitivity.	Interclock paths with skew the budget cannot absorb, or a robustness corner not defined.
C-06	Clock routes and NDR After clock routing	`route_group -all_clock_nets -reuse_existing_global_route true` `check_routes`	Clock nets carry the intended NDR and layers, and check_routes reports no violations on them.	Soft layer limits left on a few nets, or violations only on frozen clock nets.	A clock net routed at the default rule when an NDR was required, or open clock nets.
C-07	CCD and useful skew After C-02	`report_ccd_timing` `report_ccd_timing -hold` `report_clock_balance_point`	Setup and hold slack at the worst captures meet the budget, and recorded offsets are understood.	Large latency offsets on a few registers, or hold effort raised at the cost of setup.	Offsets lost because they were not saved with the session, or hold left beyond budget.
C-08	Propagated clocks and post-CTS timing After C-02	`report_timing` † `report_clock_timing -type latency`	Every intended clock is propagated and setup and hold meet the budget in every scenario.	A jump in negative slack against pre-CTS timing at clock gating endpoints, where real skew now counts.	Setup beyond budget on register paths, or a clock still ideal after CTS.
C-09	Clock power After C-03	`report_clock_power` `report_clock_power -type per_subtree` `report_clock_qor -type power`	Clock power per scenario is within the project budget, with sink pin power counted as the flow intends.	One subtree or segment carrying most of the power, or sink power counted differently from earlier runs.	Clock power beyond the project budget with no recovery step planned.

Command cheat sheet

ICC2 commands. Angle brackets are placeholders, and values shown are examples, not project limits. A dagger (†) marks a command the notes behind this book do not fully cover; it is shown without options, so confirm it with man or help in your release.

CTS setup and specification
`check_design` †	Design consistency checks before CTS. Release-specific; read the report.
`report_ignored_layers`	The routing layers currently ignored. Confirms the layer range clocks can use.
`set_clock_routing_rules -min_routing_layer <layer> -max_routing_layer <layer>`	Sets layer limits for all clock trees. Changes the session; record it.
`set_clock_routing_rules -rules <rule>`	Assigns a non-default routing rule to clock nets. Changes the session; record it.
`report_clock_balance_groups`	The clock balance groups and their offsets.
Run CTS
`clock_opt`	Full CTS and optimisation flow. Changes the design.
`clock_opt -from build_clock -to route_clock`	Builds the clock trees and routes them. Changes the design.
`clock_opt -from final_opto`	Post-CTS optimisation only. Changes the design.
`synthesize_clock_trees`	Clock tree synthesis as a separate step. Changes the design.
`synthesize_clock_trees -propagate_only`	Marks clocks propagated without building trees. Changes the session; record it.
Clock QoR reports
`report_clock_qor`	Summary of latency, skew, DRC violations, area and buffer count.
`report_clock_qor -type drc_violators`	Max transition and max capacitance violators on clock nets.
`report_clock_qor -type latency`	Longest and shortest clock paths.
`report_clock_qor -csv -output <file>`	The QoR report as a CSV file. Writes a file.
`report_clock_qor -histogram_type local_skew`	A histogram of local skew.
Skew, balance and CCD
`report_clock_qor -type local_skew`	Worst local skew per clock or skew group, with the largest and smallest cases.
`report_clock_qor -type balance_groups`	Balance group summary, with requested and achieved offsets.
`report_clock_timing -type skew`	Clock skew from the timing engine.
`report_clock_timing -type interclock_skew`	Skew between clocks.
`report_ccd_timing`	Setup slack of the worst capture and launch registers for CCD.
`report_ccd_timing -hold`	The same for hold.
Clock routes and power
`route_group -all_clock_nets -reuse_existing_global_route true`	Routes clock nets, reusing the global route. Changes the design.
`check_routes`	Routing DRC, open, antenna and voltage-area check. Writes error data.
`report_clock_power`	Clock power split by segment.
`report_clock_power -type per_subtree`	Clock power per subtree, from an ICG to its sinks.
`report_timing` †	Path timing report; confirm clock propagation and slack per scenario.