What is a basic low-power verification check (e.g. check_mv_design), and what is it looking for?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Definition
check_mv_design is a command that checks the electrical correctness of a multivoltage design against its UPF power intent — verifying that supply voltages are properly assigned, that voltage-crossing and shutdown boundaries have the necessary isolation and levelshifter cells, and that no power-state or biasing rule violations exist.
Mentor Explanation
In the overall multivoltage flow, this check sits right after cell insertion: 'load_upf' reads the intent, the optional 'create_mv_cells' inserts mapped isolation cells, level shifters, and repeaters, and then 'check_mv_design' checks electrical correctness. Some of the concrete things it catches: a supply net that hasn't been assigned an operating voltage triggers a UPF-057 error, checkable in more depth with 'check_mv_design -pg_netlist'; forward or reverse biasing violations on a power domain are reported as MV-097; and even when isolation, level-shifter, or retention insertion is deliberately suppressed via app options like 'mv.upf.skip_all_iso_insertion,' check_mv_design still reports the resulting missing cells as errors (with a couple of specific low_to_high/high_to_low/no_shift exceptions that are only warnings). It's also explicitly true that isolation cell insertion is not influenced by the power state table (PST) — it is purely directivebased via set_isolation — so any inconsistency between a PST's legal power states and the isolation strategy actually defined is exactly the kind of mismatch check_mv_design is meant to flag.
Example
If a designer defines a power state table where a switched domain's supply can go 'off' while a downstream always-on domain remains 'on,' but never wrote a set_isolation strategy for that boundary, running check_mv_design after create_mv_cells would surface the missing isolation as an error rather than silently producing a broken netlist.
Why It Matters
Every low-power design review eventually depends on this kind of automated electrical-correctness check — I want candidates to understand it's not optional polish, it's the safety net that catches the isolation/level-shifter/voltage mistakes humans make when hand-writing UPF.
Command
check_mv_design; check_mv_design -pg_netlistCommon Beginner Mistake
Treating check_mv_design as a one-time end-of-flow formality; it's meant to run right after cell insertion and again after further optimization, since new violations (like the smart-derive isolation gotcha on newly punched control ports) can appear mid-flow.
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